1a5d173| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 6.480m | 356.212ms | 45 | 50 | 90.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.100s | 176.592us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 13.877s | 19 | 20 | 95.00 | |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 16.170s | 2.422ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 13.914s | 4 | 5 | 80.00 | |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 30.373s | 18 | 20 | 90.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 13.877s | 19 | 20 | 95.00 | |
| spi_device_csr_aliasing | 13.914s | 4 | 5 | 80.00 | |||
| V1 | mem_walk | spi_device_mem_walk | 0.650s | 13.258us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 22.484s | 3 | 5 | 60.00 | |
| V1 | TOTAL | 104 | 115 | 90.43 | |||
| V2 | csb_read | spi_device_csb_read | 24.440s | 43 | 50 | 86.00 | |
| V2 | mem_parity | spi_device_mem_parity | 30.486s | 0 | 20 | 0.00 | |
| V2 | mem_cfg | spi_device_ram_cfg | 0.690s | 7.474us | 0 | 1 | 0.00 |
| V2 | tpm_read | spi_device_tpm_rw | 24.179s | 48 | 50 | 96.00 | |
| V2 | tpm_write | spi_device_tpm_rw | 24.179s | 48 | 50 | 96.00 | |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 22.314s | 44 | 50 | 88.00 | |
| spi_device_tpm_sts_read | 26.366s | 46 | 50 | 92.00 | |||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 41.060s | 26.417ms | 47 | 50 | 94.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 30.339s | 45 | 50 | 90.00 | |
| spi_device_flash_all | 4.144m | 68.809ms | 49 | 50 | 98.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 21.900s | 171.971ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 4.144m | 68.809ms | 49 | 50 | 98.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 21.900s | 171.971ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 4.144m | 68.809ms | 49 | 50 | 98.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 4.144m | 68.809ms | 49 | 50 | 98.00 |
| V2 | cmd_read_status | spi_device_intercept | 26.111s | 47 | 50 | 94.00 | |
| spi_device_flash_all | 4.144m | 68.809ms | 49 | 50 | 98.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 26.111s | 47 | 50 | 94.00 | |
| spi_device_flash_all | 4.144m | 68.809ms | 49 | 50 | 98.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 26.111s | 47 | 50 | 94.00 | |
| spi_device_flash_all | 4.144m | 68.809ms | 49 | 50 | 98.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 26.111s | 47 | 50 | 94.00 | |
| spi_device_flash_all | 4.144m | 68.809ms | 49 | 50 | 98.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 26.111s | 47 | 50 | 94.00 | |
| spi_device_flash_all | 4.144m | 68.809ms | 49 | 50 | 98.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 29.170s | 15.409ms | 46 | 50 | 92.00 |
| V2 | mailbox_command | spi_device_mailbox | 1.310m | 12.765ms | 50 | 50 | 100.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 1.310m | 12.765ms | 50 | 50 | 100.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 1.310m | 12.765ms | 50 | 50 | 100.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 37.470s | 16.402ms | 44 | 50 | 88.00 |
| spi_device_read_buffer_direct | 20.804s | 47 | 50 | 94.00 | |||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 1.310m | 12.765ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 4.144m | 68.809ms | 49 | 50 | 98.00 | ||
| V2 | quad_spi | spi_device_flash_all | 4.144m | 68.809ms | 49 | 50 | 98.00 |
| V2 | dual_spi | spi_device_flash_all | 4.144m | 68.809ms | 49 | 50 | 98.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 22.290s | 46 | 50 | 92.00 | |
| V2 | write_enable_disable | spi_device_cfg_cmd | 22.290s | 46 | 50 | 92.00 | |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 6.480m | 356.212ms | 45 | 50 | 90.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 7.145m | 163.083ms | 46 | 50 | 92.00 |
| V2 | stress_all | spi_device_stress_all | 10.704m | 1.803s | 47 | 50 | 94.00 |
| V2 | alert_test | spi_device_alert_test | 36.459s | 45 | 50 | 90.00 | |
| V2 | intr_test | spi_device_intr_test | 30.978s | 45 | 50 | 90.00 | |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 22.019s | 16 | 20 | 80.00 | |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 22.019s | 16 | 20 | 80.00 | |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.100s | 176.592us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 13.877s | 19 | 20 | 95.00 | |||
| spi_device_csr_aliasing | 13.914s | 4 | 5 | 80.00 | |||
| spi_device_same_csr_outstanding | 22.528s | 18 | 20 | 90.00 | |||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.100s | 176.592us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 13.877s | 19 | 20 | 95.00 | |||
| spi_device_csr_aliasing | 13.914s | 4 | 5 | 80.00 | |||
| spi_device_same_csr_outstanding | 22.528s | 18 | 20 | 90.00 | |||
| V2 | TOTAL | 865 | 961 | 90.01 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 0.980s | 93.272us | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 16.286s | 17 | 20 | 85.00 | |||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 16.286s | 17 | 20 | 85.00 | |
| V2S | TOTAL | 22 | 25 | 88.00 | |||
| Unmapped tests | spi_device_flash_mode_ignore_cmds | 16.781m | 1.500s | 46 | 50 | 92.00 | |
| TOTAL | 1037 | 1151 | 90.10 |
Job returned non-zero exit code has 87 failures:
Test spi_device_mem_partial_access has 2 failures.
0.spi_device_mem_partial_access.27997477519401500172280431736804601396231553528254094811159026427246249348050
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_partial_access/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 14:18 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
2.spi_device_mem_partial_access.95854276316786404316793747650891942420257076108010469828527570972477426038595
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/2.spi_device_mem_partial_access/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 14:18 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test spi_device_csr_rw has 1 failures.
0.spi_device_csr_rw.68685273194286862443405605359922279228686217748169572001981531652679399212430
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_csr_rw/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 14:18 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test spi_device_same_csr_outstanding has 1 failures.
0.spi_device_same_csr_outstanding.53620697482533273893595951918090761660300420901962063043204842360997415285633
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_same_csr_outstanding/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 14:18 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test spi_device_csb_read has 7 failures.
1.spi_device_csb_read.115091464450584602219035045867670871094819621573009054109420478732375261648902
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_csb_read/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 08:30 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
13.spi_device_csb_read.718645872688035690298820438349933771075728659412820628767498303618447394399
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/13.spi_device_csb_read/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 08:36 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 5 more failures.
Test spi_device_intercept has 3 failures.
2.spi_device_intercept.32595000227271467871847516660149393566584390880846943939992258575682571639202
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/2.spi_device_intercept/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 08:31 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
34.spi_device_intercept.32337068809206373032154964345228685765460003943068661392968036409015276977628
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/34.spi_device_intercept/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 08:46 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 1 more failures.
... and 23 more tests.
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 18 failures:
0.spi_device_mem_parity.21600090189697942835827020695734535262669219097697543424790449375383860428419
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 2834616 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[89])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 2834616 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 2834616 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[985])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
1.spi_device_mem_parity.26690950019339671644680614467307768444360539067299313541548565336950652765026
Line 83, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 4475180 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[27])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 4475180 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 4475180 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[923])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
... and 16 more failures.
Job timed out after * minutes has 8 failures:
Test spi_device_intr_test has 2 failures.
0.spi_device_intr_test.21753002419920756319812286637626199309730111336236455708606825341922778909343
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_intr_test/latest/run.log
Job timed out after 60 minutes
27.spi_device_intr_test.83011502486980764747730659158757097762243097237805930906631026870289689608903
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/27.spi_device_intr_test/latest/run.log
Job timed out after 60 minutes
Test spi_device_read_buffer_direct has 2 failures.
9.spi_device_read_buffer_direct.76387308370986011277836131751661899979010247328585946716047701115797864881690
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/9.spi_device_read_buffer_direct/latest/run.log
Job timed out after 60 minutes
14.spi_device_read_buffer_direct.29131093230453862612795560030818400439789329656135363804332217443331433582868
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/14.spi_device_read_buffer_direct/latest/run.log
Job timed out after 60 minutes
Test spi_device_flash_mode has 1 failures.
15.spi_device_flash_mode.81055429617249599660436904872655951375227328020130946248842120769540586741383
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode/latest/run.log
Job timed out after 60 minutes
Test spi_device_same_csr_outstanding has 1 failures.
15.spi_device_same_csr_outstanding.95532599153427022173910731980889712518364538346294295340271440424517327498925
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/15.spi_device_same_csr_outstanding/latest/run.log
Job timed out after 60 minutes
Test spi_device_pass_addr_payload_swap has 1 failures.
18.spi_device_pass_addr_payload_swap.907805314290721937048194903467794143455189872109079059946842406773987106249
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/18.spi_device_pass_addr_payload_swap/latest/run.log
Job timed out after 60 minutes
... and 1 more tests.
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:
0.spi_device_ram_cfg.27315542093321371615380383316618473223880273439253426464337092964053714493365
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log
UVM_ERROR @ 4775137 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc3a67f [110000111010011001111111] vs 0x0 [0])
UVM_ERROR @ 4797137 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x26938d [1001101001001110001101] vs 0x0 [0])
UVM_ERROR @ 4855137 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x93d8f2 [100100111101100011110010] vs 0x0 [0])
UVM_ERROR @ 4906137 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd6930f [110101101001001100001111] vs 0x0 [0])
UVM_ERROR @ 4934137 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1f2949 [111110010100101001001] vs 0x0 [0])
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
46.spi_device_flash_mode_ignore_cmds.27529831374834393120212232390547112162506430282977020824943568969769240211602
Line 118, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest/run.log
UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed most likely because its dependent job failed. has 1 failures: