1a5d173| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 5.408m | 73.657ms | 46 | 50 | 92.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.280s | 284.854us | 4 | 5 | 80.00 |
| V1 | csr_rw | spi_device_csr_rw | 15.602s | 19 | 20 | 95.00 | |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 25.090s | 10.403ms | 4 | 5 | 80.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 15.090s | 4.540ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 20.083s | 16 | 20 | 80.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 15.602s | 19 | 20 | 95.00 | |
| spi_device_csr_aliasing | 15.090s | 4.540ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.700s | 33.293us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 18.050s | 3 | 5 | 60.00 | |
| V1 | TOTAL | 102 | 115 | 88.70 | |||
| V2 | csb_read | spi_device_csb_read | 28.575s | 49 | 50 | 98.00 | |
| V2 | mem_parity | spi_device_mem_parity | 17.956s | 19 | 20 | 95.00 | |
| V2 | mem_cfg | spi_device_ram_cfg | 0.660s | 26.149us | 1 | 1 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 24.814s | 45 | 50 | 90.00 | |
| V2 | tpm_write | spi_device_tpm_rw | 24.814s | 45 | 50 | 90.00 | |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 33.668s | 41 | 50 | 82.00 | |
| spi_device_tpm_sts_read | 23.981s | 47 | 50 | 94.00 | |||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 25.730s | 17.321ms | 45 | 50 | 90.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 15.602s | 48 | 50 | 96.00 | |
| spi_device_flash_all | 5.537m | 366.194ms | 48 | 50 | 96.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 21.980s | 66.675ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 5.537m | 366.194ms | 48 | 50 | 96.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 21.980s | 66.675ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 5.537m | 366.194ms | 48 | 50 | 96.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 5.537m | 366.194ms | 48 | 50 | 96.00 |
| V2 | cmd_read_status | spi_device_intercept | 24.135s | 41 | 50 | 82.00 | |
| spi_device_flash_all | 5.537m | 366.194ms | 48 | 50 | 96.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 24.135s | 41 | 50 | 82.00 | |
| spi_device_flash_all | 5.537m | 366.194ms | 48 | 50 | 96.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 24.135s | 41 | 50 | 82.00 | |
| spi_device_flash_all | 5.537m | 366.194ms | 48 | 50 | 96.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 24.135s | 41 | 50 | 82.00 | |
| spi_device_flash_all | 5.537m | 366.194ms | 48 | 50 | 96.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 24.135s | 41 | 50 | 82.00 | |
| spi_device_flash_all | 5.537m | 366.194ms | 48 | 50 | 96.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 24.414s | 46 | 50 | 92.00 | |
| V2 | mailbox_command | spi_device_mailbox | 1.366m | 11.824ms | 48 | 50 | 96.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 1.366m | 11.824ms | 48 | 50 | 96.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 1.366m | 11.824ms | 48 | 50 | 96.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 38.550s | 19.005ms | 42 | 50 | 84.00 |
| spi_device_read_buffer_direct | 24.780s | 45 | 50 | 90.00 | |||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 1.366m | 11.824ms | 48 | 50 | 96.00 |
| spi_device_flash_all | 5.537m | 366.194ms | 48 | 50 | 96.00 | ||
| V2 | quad_spi | spi_device_flash_all | 5.537m | 366.194ms | 48 | 50 | 96.00 |
| V2 | dual_spi | spi_device_flash_all | 5.537m | 366.194ms | 48 | 50 | 96.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 24.385s | 46 | 50 | 92.00 | |
| V2 | write_enable_disable | spi_device_cfg_cmd | 24.385s | 46 | 50 | 92.00 | |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 5.408m | 73.657ms | 46 | 50 | 92.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 5.461m | 128.622ms | 48 | 50 | 96.00 |
| V2 | stress_all | spi_device_stress_all | 7.826m | 196.640ms | 45 | 50 | 90.00 |
| V2 | alert_test | spi_device_alert_test | 21.811s | 45 | 50 | 90.00 | |
| V2 | intr_test | spi_device_intr_test | 26.491s | 47 | 50 | 94.00 | |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 24.360s | 18 | 20 | 90.00 | |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 24.360s | 18 | 20 | 90.00 | |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.280s | 284.854us | 4 | 5 | 80.00 |
| spi_device_csr_rw | 15.602s | 19 | 20 | 95.00 | |||
| spi_device_csr_aliasing | 15.090s | 4.540ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 21.983s | 19 | 20 | 95.00 | |||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.280s | 284.854us | 4 | 5 | 80.00 |
| spi_device_csr_rw | 15.602s | 19 | 20 | 95.00 | |||
| spi_device_csr_aliasing | 15.090s | 4.540ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 21.983s | 19 | 20 | 95.00 | |||
| V2 | TOTAL | 879 | 961 | 91.47 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 26.616s | 4 | 5 | 80.00 | |
| spi_device_tl_intg_err | 15.110s | 2.955ms | 19 | 20 | 95.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 15.110s | 2.955ms | 19 | 20 | 95.00 |
| V2S | TOTAL | 23 | 25 | 92.00 | |||
| Unmapped tests | spi_device_flash_mode_ignore_cmds | 4.486m | 149.985ms | 49 | 50 | 98.00 | |
| TOTAL | 1053 | 1151 | 91.49 |
Job returned non-zero exit code has 87 failures:
Test spi_device_intr_test has 3 failures.
0.spi_device_intr_test.8086914325599714501768138684088061873005260507850321188961793048238434764898
Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/0.spi_device_intr_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 03:14 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
3.spi_device_intr_test.51279424493207258388503276240220025561928977573593384311184033426345950677677
Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/3.spi_device_intr_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 03:15 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 1 more failures.
Test spi_device_same_csr_outstanding has 1 failures.
0.spi_device_same_csr_outstanding.57264518912279460441006146433758906642450689612277830063965137212319345495336
Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/0.spi_device_same_csr_outstanding/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 03:14 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test spi_device_csb_read has 1 failures.
1.spi_device_csb_read.95568874741020657905636338281071841811870046797783702105191438193055314433885
Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/1.spi_device_csb_read/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 06:35 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test spi_device_tpm_read_hw_reg has 9 failures.
1.spi_device_tpm_read_hw_reg.53873134548677034494642282350052507404136894132933742679997972406654583130091
Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/1.spi_device_tpm_read_hw_reg/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 06:35 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
10.spi_device_tpm_read_hw_reg.105932571998703720054095058109219679857217397141453484766988111856000065240516
Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/10.spi_device_tpm_read_hw_reg/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 06:38 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 7 more failures.
Test spi_device_stress_all has 4 failures.
1.spi_device_stress_all.1693436822049278075918911130954655737786643333467150821142127140333208131590
Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/1.spi_device_stress_all/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 06:35 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
13.spi_device_stress_all.92398468638310830898658394849201593290295764493067134657185746838233435215472
Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/13.spi_device_stress_all/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 06:39 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 2 more failures.
... and 25 more tests.
Job timed out after * minutes has 12 failures:
Test spi_device_stress_all has 1 failures.
0.spi_device_stress_all.81984282641164911547992306703879452366124095099116753172710816361679154698868
Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/0.spi_device_stress_all/latest/run.log
Job timed out after 180 minutes
Test spi_device_mem_partial_access has 1 failures.
0.spi_device_mem_partial_access.79714430166191504731045085616550450690430770123859131075211070171752253553064
Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/0.spi_device_mem_partial_access/latest/run.log
Job timed out after 60 minutes
Test spi_device_csr_hw_reset has 1 failures.
3.spi_device_csr_hw_reset.38930032720145275690954661159499112571876260578794648936633417224734471326139
Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/3.spi_device_csr_hw_reset/latest/run.log
Job timed out after 60 minutes
Test spi_device_pass_addr_payload_swap has 2 failures.
6.spi_device_pass_addr_payload_swap.72265974875772001436101631344231708433711508912340806692226762728036208366685
Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/6.spi_device_pass_addr_payload_swap/latest/run.log
Job timed out after 60 minutes
8.spi_device_pass_addr_payload_swap.95743638674631420198383342361832270403444716721262645370879825452048276128931
Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/8.spi_device_pass_addr_payload_swap/latest/run.log
Job timed out after 60 minutes
Test spi_device_intercept has 2 failures.
8.spi_device_intercept.30839227085905133370065181929394830286001688419898812991500953878423348114520
Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/8.spi_device_intercept/latest/run.log
Job timed out after 60 minutes
23.spi_device_intercept.103948101457066102813738477547815708089562176108537152851425623839093669345694
Log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/23.spi_device_intercept/latest/run.log
Job timed out after 60 minutes
... and 4 more tests.
Job killed most likely because its dependent job failed. has 1 failures: