SPI_HOST Simulation Results

Sunday September 21 2025 01:07:51 UTC

GitHub Revision: 1a5d173

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 42.000s 5 50 10.00
V1 csr_hw_reset spi_host_csr_hw_reset 50.000s 3 5 60.00
V1 csr_rw spi_host_csr_rw 46.000s 1 20 5.00
V1 csr_bit_bash spi_host_csr_bit_bash 1.133m 1 5 20.00
V1 csr_aliasing spi_host_csr_aliasing 52.000s 0 5 0.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 52.000s 1 20 5.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 46.000s 1 20 5.00
spi_host_csr_aliasing 52.000s 0 5 0.00
V1 mem_walk spi_host_mem_walk 1.017m 1 5 20.00
V1 mem_partial_access spi_host_mem_partial_access 53.000s 0 5 0.00
V1 TOTAL 12 115 10.43
V2 performance spi_host_performance 46.000s 1 50 2.00
V2 error_event_intr spi_host_overflow_underflow 43.000s 3 50 6.00
spi_host_error_cmd 42.000s 0 50 0.00
spi_host_event 47.000s 3 50 6.00
V2 clock_rate spi_host_speed 47.000s 1 50 2.00
V2 speed spi_host_speed 47.000s 1 50 2.00
V2 chip_select_timing spi_host_speed 47.000s 1 50 2.00
V2 sw_reset spi_host_sw_reset 42.000s 3 50 6.00
V2 passthrough_mode spi_host_passthrough_mode 47.000s 2 50 4.00
V2 cpol_cpha spi_host_speed 47.000s 1 50 2.00
V2 full_cycle spi_host_speed 47.000s 1 50 2.00
V2 duplex spi_host_smoke 42.000s 5 50 10.00
V2 tx_rx_only spi_host_smoke 42.000s 5 50 10.00
V2 stress_all spi_host_stress_all 1.317m 9.449ms 4 50 8.00
V2 spien spi_host_spien 42.000s 2 50 4.00
V2 stall spi_host_status_stall 1.150m 8.298ms 3 50 6.00
V2 Idlecsbactive spi_host_idlecsbactive 47.000s 4 50 8.00
V2 data_fifo_status spi_host_overflow_underflow 43.000s 3 50 6.00
V2 alert_test spi_host_alert_test 50.000s 0 50 0.00
V2 intr_test spi_host_intr_test 1.033m 1 50 2.00
V2 tl_d_oob_addr_access spi_host_tl_errors 57.000s 1 20 5.00
V2 tl_d_illegal_access spi_host_tl_errors 57.000s 1 20 5.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 50.000s 3 5 60.00
spi_host_csr_rw 46.000s 1 20 5.00
spi_host_csr_aliasing 52.000s 0 5 0.00
spi_host_same_csr_outstanding 58.000s 2 20 10.00
V2 tl_d_partial_access spi_host_csr_hw_reset 50.000s 3 5 60.00
spi_host_csr_rw 46.000s 1 20 5.00
spi_host_csr_aliasing 52.000s 0 5 0.00
spi_host_same_csr_outstanding 58.000s 2 20 10.00
V2 TOTAL 30 690 4.35
V2S tl_intg_err spi_host_tl_intg_err 46.000s 3 20 15.00
spi_host_sec_cm 38.000s 1 5 20.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 46.000s 3 20 15.00
V2S TOTAL 4 25 16.00
Unmapped tests spi_host_upper_range_clkdiv 3.983m 14.521ms 1 10 10.00
TOTAL 47 840 5.60

Failure Buckets