1a5d173| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 57.100s | 1.458ms | 40 | 50 | 80.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.640s | 45.951us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 34.603s | 18 | 20 | 90.00 | |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 20.680s | 4 | 5 | 80.00 | |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.690s | 21.906us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 24.492s | 18 | 20 | 90.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 34.603s | 18 | 20 | 90.00 | |
| sram_ctrl_csr_aliasing | 0.690s | 21.906us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 4.140m | 86.277ms | 39 | 50 | 78.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 1.952m | 32.170ms | 38 | 50 | 76.00 |
| V1 | TOTAL | 167 | 205 | 81.46 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 13.548m | 100.996ms | 41 | 50 | 82.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 6.296m | 26.345ms | 41 | 50 | 82.00 |
| V2 | bijection | sram_ctrl_bijection | 33.766m | 662.983ms | 42 | 50 | 84.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 14.639m | 19.930ms | 42 | 50 | 84.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 1.064m | 31.511ms | 45 | 50 | 90.00 |
| V2 | executable | sram_ctrl_executable | 13.506m | 46.278ms | 45 | 50 | 90.00 |
| V2 | partial_access | sram_ctrl_partial_access | 57.060s | 950.382us | 42 | 50 | 84.00 |
| sram_ctrl_partial_access_b2b | 6.561m | 69.826ms | 42 | 50 | 84.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 56.430s | 805.399us | 43 | 50 | 86.00 |
| sram_ctrl_throughput_w_partial_write | 59.040s | 3.259ms | 43 | 50 | 86.00 | ||
| sram_ctrl_throughput_w_readback | 1.028m | 1.850ms | 44 | 50 | 88.00 | ||
| V2 | regwen | sram_ctrl_regwen | 12.641m | 24.081ms | 42 | 50 | 84.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 34.737s | 41 | 50 | 82.00 | |
| V2 | stress_all | sram_ctrl_stress_all | 1.634h | 303.933ms | 44 | 50 | 88.00 |
| V2 | alert_test | sram_ctrl_alert_test | 26.595s | 45 | 50 | 90.00 | |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 2.910s | 240.716us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 2.910s | 240.716us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.640s | 45.951us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 34.603s | 18 | 20 | 90.00 | |||
| sram_ctrl_csr_aliasing | 0.690s | 21.906us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 13.922s | 19 | 20 | 95.00 | |||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.640s | 45.951us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 34.603s | 18 | 20 | 90.00 | |||
| sram_ctrl_csr_aliasing | 0.690s | 21.906us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 13.922s | 19 | 20 | 95.00 | |||
| V2 | TOTAL | 681 | 790 | 86.20 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 35.630s | 78.005ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 0.650s | 21.721us | 0 | 5 | 0.00 |
| sram_ctrl_tl_intg_err | 17.976s | 18 | 20 | 90.00 | |||
| V2S | prim_count_check | sram_ctrl_sec_cm | 0.650s | 21.721us | 0 | 5 | 0.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 17.976s | 18 | 20 | 90.00 | |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 12.641m | 24.081ms | 42 | 50 | 84.00 |
| V2S | sec_cm_readback_config_regwen | sram_ctrl_regwen | 12.641m | 24.081ms | 42 | 50 | 84.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 34.603s | 18 | 20 | 90.00 | |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 13.506m | 46.278ms | 45 | 50 | 90.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 13.506m | 46.278ms | 45 | 50 | 90.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 13.506m | 46.278ms | 45 | 50 | 90.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 1.064m | 31.511ms | 45 | 50 | 90.00 |
| V2S | sec_cm_prim_ram_ctrl_mubi | sram_ctrl_mubi_enc_err | 30.307s | 33 | 50 | 66.00 | |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 35.630s | 78.005ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_readback | sram_ctrl_readback_err | 32.688s | 34 | 50 | 68.00 | |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 57.100s | 1.458ms | 40 | 50 | 80.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 57.100s | 1.458ms | 40 | 50 | 80.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 13.506m | 46.278ms | 45 | 50 | 90.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 0.650s | 21.721us | 0 | 5 | 0.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 1.064m | 31.511ms | 45 | 50 | 90.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 0.650s | 21.721us | 0 | 5 | 0.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 0.650s | 21.721us | 0 | 5 | 0.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 57.100s | 1.458ms | 40 | 50 | 80.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 0.650s | 21.721us | 0 | 5 | 0.00 |
| V2S | TOTAL | 105 | 145 | 72.41 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 1.595m | 11.347ms | 42 | 50 | 84.00 |
| V3 | TOTAL | 42 | 50 | 84.00 | |||
| TOTAL | 995 | 1190 | 83.61 |
Job returned non-zero exit code has 152 failures:
Test sram_ctrl_partial_access_b2b has 7 failures.
0.sram_ctrl_partial_access_b2b.92207870816383027717409617508317056833800982323685011315695401696495843675770
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access_b2b/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:49 2025
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
5.sram_ctrl_partial_access_b2b.109858633125185399358581520864222709588998076352213959318177870316677436735028
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access_b2b/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:53 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 5 more failures.
Test sram_ctrl_csr_rw has 2 failures.
0.sram_ctrl_csr_rw.38773972641707361008330634826414347555811702162510400156973106366052478607763
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_rw/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:38 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
1.sram_ctrl_csr_rw.96699852194732530204348358586023630631997299066517470811334182200339530404558
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_rw/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:38 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test sram_ctrl_same_csr_outstanding has 1 failures.
1.sram_ctrl_same_csr_outstanding.38508503005894654046724239093133022642198285219500443933291032203321901275233
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:38 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test sram_ctrl_max_throughput has 5 failures.
2.sram_ctrl_max_throughput.77806037222691522739540333403149829963746832601423450470184371594557463730511
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_max_throughput/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:49 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
10.sram_ctrl_max_throughput.68511259656871269189088877394114859467658659089111579830639630383603677477620
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/10.sram_ctrl_max_throughput/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 02:01 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 3 more failures.
Test sram_ctrl_access_during_key_req has 7 failures.
2.sram_ctrl_access_during_key_req.75251416395951397704907928538560927272343814751996876930836920217612674224461
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_access_during_key_req/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:49 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
4.sram_ctrl_access_during_key_req.29586573973392923333932932006307862606550563729798347889144069132009583653397
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_access_during_key_req/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:51 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 5 more failures.
... and 22 more tests.
Job timed out after * minutes has 19 failures:
Test sram_ctrl_mem_partial_access has 3 failures.
4.sram_ctrl_mem_partial_access.40773398253026104193419577569042325293091900784705200659196533136496886595686
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_mem_partial_access/latest/run.log
Job timed out after 60 minutes
9.sram_ctrl_mem_partial_access.84045094364903025137248838520369452624739179358683130317800346646280667016783
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/9.sram_ctrl_mem_partial_access/latest/run.log
Job timed out after 60 minutes
... and 1 more failures.
Test sram_ctrl_max_throughput has 2 failures.
7.sram_ctrl_max_throughput.46628322071805819532057670324931506071234353256488576892911074042911856592624
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_max_throughput/latest/run.log
Job timed out after 60 minutes
32.sram_ctrl_max_throughput.33497519602469246061839447855222475346098201842816674668388367035773982216467
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/32.sram_ctrl_max_throughput/latest/run.log
Job timed out after 60 minutes
Test sram_ctrl_stress_pipeline has 3 failures.
12.sram_ctrl_stress_pipeline.95500328879582004550749608419993938344470337065840683786384748870637981631931
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_pipeline/latest/run.log
Job timed out after 60 minutes
27.sram_ctrl_stress_pipeline.43845634497734849035668296117817366640769462861017941331523777454605156023074
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_pipeline/latest/run.log
Job timed out after 60 minutes
... and 1 more failures.
Test sram_ctrl_readback_err has 1 failures.
12.sram_ctrl_readback_err.81943232120087989437066821329866025950345978736373894083808469949082294687678
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/12.sram_ctrl_readback_err/latest/run.log
Job timed out after 60 minutes
Test sram_ctrl_smoke has 1 failures.
13.sram_ctrl_smoke.25821162650673027635130278866160414085589765120503830422600912166645662069361
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/13.sram_ctrl_smoke/latest/run.log
Job timed out after 60 minutes
... and 7 more tests.
Offending 'reqfifo_rvalid' has 11 failures:
1.sram_ctrl_mubi_enc_err.71693984129370531977437903344456574386940394443410017035760890817151702019276
Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_mubi_enc_err/latest/run.log
Offending 'reqfifo_rvalid'
UVM_ERROR @ 664634961 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 664634961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.sram_ctrl_mubi_enc_err.43597393486458757587204050727294059834264603690534097008329508771412467948933
Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/10.sram_ctrl_mubi_enc_err/latest/run.log
Offending 'reqfifo_rvalid'
UVM_ERROR @ 3461622527 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 3461622527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 7 failures:
5.sram_ctrl_readback_err.39097822834240839854772445958099986758922673209485556774916435031762142293013
Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/5.sram_ctrl_readback_err/latest/run.log
UVM_ERROR @ 688434535 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3c) != exp (0x73)
UVM_INFO @ 688434535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.sram_ctrl_readback_err.98273850390668434952613834217868794187582713647336664547100434558611037187318
Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/10.sram_ctrl_readback_err/latest/run.log
UVM_ERROR @ 661084097 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x21) != exp (0x76)
UVM_INFO @ 661084097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:
0.sram_ctrl_sec_cm.43687550804917232678336341246995143003847174959765790943358134043764612816809
Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
UVM_ERROR @ 1719559 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 1719559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.sram_ctrl_sec_cm.73713019969062608813502554730351038783424188867676407128673374191592368687623
Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log
UVM_ERROR @ 7014116 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 7014116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '(!$isunknown(rdata_o))' has 2 failures:
1.sram_ctrl_sec_cm.18924161136738619762165843581359222070488198968580460780661302637997811169371
Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 2260533 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 2260533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.sram_ctrl_sec_cm.41626745780235141681699150070152901157029662941091567558826405544096065840555
Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 3821819 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 3821819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:945) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
3.sram_ctrl_stress_all_with_rand_reset.9714323122250463072760769230428628547588019810971922026607596498447385177518
Line 103, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4571701879 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4571701879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:
4.sram_ctrl_csr_mem_rw_with_rand_reset.13973919555582321654607537363869849449628698033432580792220849597734658193698
Line 93, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_FATAL @ 10004533987 ps: (sram_ctrl_base_vseq.sv:168) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
UVM_INFO @ 10004533987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---