1a5d173| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 1.015m | 679.375us | 44 | 50 | 88.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.750s | 15.161us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 15.946s | 18 | 20 | 90.00 | |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 1.800s | 262.461us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.780s | 23.278us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 20.442s | 18 | 20 | 90.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 15.946s | 18 | 20 | 90.00 | |
| sram_ctrl_csr_aliasing | 0.780s | 23.278us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 26.269s | 44 | 50 | 88.00 | |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 18.240s | 46 | 50 | 92.00 | |
| V1 | TOTAL | 185 | 205 | 90.24 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 12.119m | 49.193ms | 41 | 50 | 82.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 5.001m | 4.268ms | 47 | 50 | 94.00 |
| V2 | bijection | sram_ctrl_bijection | 58.210s | 5.639ms | 38 | 50 | 76.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 14.496m | 23.886ms | 41 | 50 | 82.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 39.067s | 44 | 50 | 88.00 | |
| V2 | executable | sram_ctrl_executable | 16.406m | 4.314ms | 40 | 50 | 80.00 |
| V2 | partial_access | sram_ctrl_partial_access | 1.059m | 2.926ms | 46 | 50 | 92.00 |
| sram_ctrl_partial_access_b2b | 6.764m | 22.216ms | 43 | 50 | 86.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 58.730s | 221.638us | 45 | 50 | 90.00 |
| sram_ctrl_throughput_w_partial_write | 1.016m | 660.019us | 42 | 50 | 84.00 | ||
| sram_ctrl_throughput_w_readback | 59.900s | 573.005us | 43 | 50 | 86.00 | ||
| V2 | regwen | sram_ctrl_regwen | 13.429m | 13.097ms | 42 | 50 | 84.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 30.611s | 45 | 50 | 90.00 | |
| V2 | stress_all | sram_ctrl_stress_all | 47.342m | 87.980ms | 38 | 50 | 76.00 |
| V2 | alert_test | sram_ctrl_alert_test | 30.418s | 39 | 50 | 78.00 | |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 28.822s | 17 | 20 | 85.00 | |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 28.822s | 17 | 20 | 85.00 | |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.750s | 15.161us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 15.946s | 18 | 20 | 90.00 | |||
| sram_ctrl_csr_aliasing | 0.780s | 23.278us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 33.179s | 17 | 20 | 85.00 | |||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.750s | 15.161us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 15.946s | 18 | 20 | 90.00 | |||
| sram_ctrl_csr_aliasing | 0.780s | 23.278us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 33.179s | 17 | 20 | 85.00 | |||
| V2 | TOTAL | 668 | 790 | 84.56 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 19.862s | 15 | 20 | 75.00 | |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 16.039s | 0 | 5 | 0.00 | |
| sram_ctrl_tl_intg_err | 2.160s | 1.185ms | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 16.039s | 0 | 5 | 0.00 | |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 2.160s | 1.185ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 13.429m | 13.097ms | 42 | 50 | 84.00 |
| V2S | sec_cm_readback_config_regwen | sram_ctrl_regwen | 13.429m | 13.097ms | 42 | 50 | 84.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 15.946s | 18 | 20 | 90.00 | |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 16.406m | 4.314ms | 40 | 50 | 80.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 16.406m | 4.314ms | 40 | 50 | 80.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 16.406m | 4.314ms | 40 | 50 | 80.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 39.067s | 44 | 50 | 88.00 | |
| V2S | sec_cm_prim_ram_ctrl_mubi | sram_ctrl_mubi_enc_err | 16.413s | 37 | 50 | 74.00 | |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 19.862s | 15 | 20 | 75.00 | |
| V2S | sec_cm_mem_readback | sram_ctrl_readback_err | 28.377s | 31 | 50 | 62.00 | |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 1.015m | 679.375us | 44 | 50 | 88.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 1.015m | 679.375us | 44 | 50 | 88.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 16.406m | 4.314ms | 40 | 50 | 80.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 16.039s | 0 | 5 | 0.00 | |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 39.067s | 44 | 50 | 88.00 | |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 16.039s | 0 | 5 | 0.00 | |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 16.039s | 0 | 5 | 0.00 | |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 1.015m | 679.375us | 44 | 50 | 88.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 16.039s | 0 | 5 | 0.00 | |
| V2S | TOTAL | 103 | 145 | 71.03 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 4.966m | 8.839ms | 42 | 50 | 84.00 |
| V3 | TOTAL | 42 | 50 | 84.00 | |||
| TOTAL | 998 | 1190 | 83.87 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.64 | 99.07 | 92.90 | 85.37 | 100.00 | 97.98 | 95.79 | 98.33 |
Job returned non-zero exit code has 154 failures:
0.sram_ctrl_executable.58383065327163489888433603393050050284881229757437380944299197647899189635865
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_executable/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 10:47 2025
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
10.sram_ctrl_executable.70347941460415579476685529638491486243855944175419732271752017986365486934155
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/10.sram_ctrl_executable/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 10:55 2025
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 6 more failures.
1.sram_ctrl_multiple_keys.75832877796711821606506875422026387863716788697257814336334540670455324813811
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_multiple_keys/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 10:47 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
3.sram_ctrl_multiple_keys.42906944012449021179757722400188450029130681291279760346001050105901431141206
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_multiple_keys/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 10:49 2025
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 7 more failures.
1.sram_ctrl_lc_escalation.66876911395210774764612128767689897270789407472396430843295549092260481857932
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_lc_escalation/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 10:48 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
14.sram_ctrl_lc_escalation.106635171116194919601018153889029817583831165641843199328058419156847388658249
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/14.sram_ctrl_lc_escalation/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 10:59 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 2 more failures.
1.sram_ctrl_mubi_enc_err.72710524959305370955923090141612043052019346856073537787880677296271321870883
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mubi_enc_err/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 10:48 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
4.sram_ctrl_mubi_enc_err.24140990355067513853076509593389059650693494687903856663147101142427784240977
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mubi_enc_err/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 10:51 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 2 more failures.
1.sram_ctrl_tl_errors.28882341498346923817704847051966496719992314977616384040948801434128677215314
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_errors/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 10:44 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
5.sram_ctrl_tl_errors.90677425821527319698472293757418689324759412667026569843623812454103661192818
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_errors/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 10:45 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 1 more failures.
Job timed out after * minutes has 13 failures:
Test sram_ctrl_readback_err has 1 failures.
2.sram_ctrl_readback_err.95785238721956047371219966094698427053968402419396268866543891812710961988559
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_readback_err/latest/run.log
Job timed out after 60 minutes
Test sram_ctrl_alert_test has 1 failures.
3.sram_ctrl_alert_test.115544621616267190980792520227626602947595304486853780514140388517544781156516
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_alert_test/latest/run.log
Job timed out after 60 minutes
Test sram_ctrl_mem_partial_access has 1 failures.
5.sram_ctrl_mem_partial_access.64150735171435067676240810687172798255247697655783886470946087876013653029613
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_partial_access/latest/run.log
Job timed out after 60 minutes
Test sram_ctrl_csr_rw has 1 failures.
6.sram_ctrl_csr_rw.86735520847410836953648168859843897190531171338115834747097152684583199445467
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_rw/latest/run.log
Job timed out after 60 minutes
Test sram_ctrl_lc_escalation has 2 failures.
10.sram_ctrl_lc_escalation.61195686072387117288340803298399917684315098108291531755267272792001398077937
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/10.sram_ctrl_lc_escalation/latest/run.log
Job timed out after 60 minutes
30.sram_ctrl_lc_escalation.7774670363188606575132316603807629203349671345265796396887469133891779819358
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/30.sram_ctrl_lc_escalation/latest/run.log
Job timed out after 60 minutes
... and 5 more tests.
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 11 failures:
0.sram_ctrl_readback_err.99065489627547728882082775212529925634541501462115316528673145287988137441647
Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log
UVM_ERROR @ 46579277 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3e) != exp (0x51)
UVM_INFO @ 46579277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.sram_ctrl_readback_err.88108245954417407720443382788632659944479101929945805140150020804248731401612
Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_readback_err/latest/run.log
UVM_ERROR @ 107090218 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x30) != exp (0x68)
UVM_INFO @ 107090218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
Offending 'reqfifo_rvalid' has 8 failures:
11.sram_ctrl_mubi_enc_err.66806790259339972947678292852729479752041592448268229284465085509778439495226
Line 111, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mubi_enc_err/latest/run.log
Offending 'reqfifo_rvalid'
UVM_ERROR @ 29217642 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 29217642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.sram_ctrl_mubi_enc_err.38806687769592188605640167707007623755297174664666843422525197690364824162030
Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mubi_enc_err/latest/run.log
Offending 'reqfifo_rvalid'
UVM_ERROR @ 73887538 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 73887538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:
0.sram_ctrl_sec_cm.83516722638624037731318824006141523255918414744959014822624202368030321970319
Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
UVM_ERROR @ 7498681 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 7498681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.sram_ctrl_sec_cm.34706133585931173081769070649755931553528086423033038014389489524100228570109
Line 106, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log
UVM_ERROR @ 2200056 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 2200056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))' has 2 failures:
1.sram_ctrl_sec_cm.79592324101347135868835317826393850588738167514266695170400764034322688977268
Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 15604651 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 15604651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.sram_ctrl_sec_cm.83247704407992880014689041259728293249938470928925362734637979018390483093099
Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 11313045 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 11313045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
4.sram_ctrl_csr_mem_rw_with_rand_reset.114800034251487329878884985120528801066865018624360131200629271585612332834767
Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 46786203 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
UVM_INFO @ 46786203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4920) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
36.sram_ctrl_mubi_enc_err.82838758102006206224073675935358973187844520177454002557388089702396690706118
Line 110, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mubi_enc_err/latest/run.log
UVM_ERROR @ 101944852 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4920) { a_addr: 'h54d6669c a_data: 'h6f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hab a_opcode: 'h1 a_user: 'h2558d d_param: 'h0 d_source: 'hab d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 101944852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---