1a5d173| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 30.464s | 47 | 50 | 94.00 | |
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 29.000s | 42 | 50 | 84.00 | |
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 30.619s | 3 | 5 | 60.00 | |
| V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 4.950s | 2.545ms | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 8.150s | 4.008ms | 5 | 5 | 100.00 |
| V1 | csr_rw | sysrst_ctrl_csr_rw | 26.664s | 18 | 20 | 90.00 | |
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 2.095m | 75.550ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 6.490s | 2.594ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 31.013s | 17 | 20 | 85.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 26.664s | 18 | 20 | 90.00 | |
| sysrst_ctrl_csr_aliasing | 6.490s | 2.594ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 147 | 165 | 89.09 | |||
| V2 | combo_detect | sysrst_ctrl_combo_detect | 5.694m | 199.782ms | 46 | 50 | 92.00 |
| V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 3.481m | 127.216ms | 82 | 100 | 82.00 |
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 8.262m | 317.826ms | 48 | 50 | 96.00 |
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 18.289m | 626.095ms | 39 | 50 | 78.00 |
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 22.282s | 48 | 50 | 96.00 | |
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 33.152s | 41 | 50 | 82.00 | |
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 18.303m | 672.356ms | 43 | 50 | 86.00 |
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 24.448s | 48 | 50 | 96.00 | |
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 6.167m | 1.499s | 38 | 50 | 76.00 |
| V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 34.280s | 40.028ms | 2 | 2 | 100.00 |
| V2 | stress_all | sysrst_ctrl_stress_all | 5.500m | 215.580ms | 45 | 50 | 90.00 |
| V2 | alert_test | sysrst_ctrl_alert_test | 37.101s | 46 | 50 | 92.00 | |
| V2 | intr_test | sysrst_ctrl_intr_test | 24.027s | 42 | 50 | 84.00 | |
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 20.029s | 18 | 20 | 90.00 | |
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 20.029s | 18 | 20 | 90.00 | |
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 8.150s | 4.008ms | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 26.664s | 18 | 20 | 90.00 | |||
| sysrst_ctrl_csr_aliasing | 6.490s | 2.594ms | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 22.960s | 7.851ms | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 8.150s | 4.008ms | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 26.664s | 18 | 20 | 90.00 | |||
| sysrst_ctrl_csr_aliasing | 6.490s | 2.594ms | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 22.960s | 7.851ms | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 605 | 692 | 87.43 | |||
| V2S | tl_intg_err | sysrst_ctrl_sec_cm | 1.182m | 42.012ms | 3 | 5 | 60.00 |
| sysrst_ctrl_tl_intg_err | 1.360m | 42.463ms | 19 | 20 | 95.00 | ||
| V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 1.360m | 42.463ms | 19 | 20 | 95.00 |
| V2S | TOTAL | 22 | 25 | 88.00 | |||
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 13.854s | 46 | 50 | 92.00 | |
| V3 | TOTAL | 46 | 50 | 92.00 | |||
| TOTAL | 820 | 932 | 87.98 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.57 | 99.31 | 97.52 | 100.00 | 92.95 | 99.41 | 97.89 | 81.88 |
Job returned non-zero exit code has 88 failures:
Test sysrst_ctrl_in_out_inverted has 8 failures.
0.sysrst_ctrl_in_out_inverted.90020651281880357324817862253590413948097417449011496227875871259320841598261
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_in_out_inverted/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 04:18 2025
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
2.sysrst_ctrl_in_out_inverted.100844085850839809887801254679606621455712222419081861342417731653157295458839
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_in_out_inverted/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 04:18 2025
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 6 more failures.
Test sysrst_ctrl_ec_pwr_on_rst has 6 failures.
0.sysrst_ctrl_ec_pwr_on_rst.98685919056094387934359729641701180640748236348194578171621342458745514975973
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 04:18 2025
Feature removed during lmreread, or wrong
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Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
5.sysrst_ctrl_ec_pwr_on_rst.16622987174218137479392523070380110770546816237631274236633227326212379427154
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 04:20 2025
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 4 more failures.
Test sysrst_ctrl_csr_mem_rw_with_rand_reset has 3 failures.
0.sysrst_ctrl_csr_mem_rw_with_rand_reset.44502455476603217695844032390388999947458553856246165922961074787767268154153
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:34 2025
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
1.sysrst_ctrl_csr_mem_rw_with_rand_reset.103964126578569070670561220835540823349090723077677346017145826235611825001235
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:34 2025
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 1 more failures.
Test sysrst_ctrl_sec_cm has 2 failures.
1.sysrst_ctrl_sec_cm.75167910633393342456303487872946776396120732195569510838442535817464007405287
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_sec_cm/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 04:18 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
3.sysrst_ctrl_sec_cm.28729116354722002374759523607807101222558164456003080607482416053180243303529
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_sec_cm/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 04:19 2025
Feature removed during lmreread, or wrong
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Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test sysrst_ctrl_intr_test has 7 failures.
2.sysrst_ctrl_intr_test.71480089415482688578321826427273849582517605937098486272324178555967228683328
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_intr_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:34 2025
Feature removed during lmreread, or wrong
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Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
5.sysrst_ctrl_intr_test.46448436732365050664787102789200626939735506821060158081126589959560909074053
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_intr_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 21 01:34 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 5 more failures.
... and 17 more tests.
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 9 failures:
Test sysrst_ctrl_ultra_low_pwr has 4 failures.
12.sysrst_ctrl_ultra_low_pwr.55071551520375143592956020556793429202308792665142769236509943063913683700495
Line 382, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 4358089333 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 4358194596 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4358194596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.sysrst_ctrl_ultra_low_pwr.80365251811689718469416056210703256938147913796889168708279225489372264520499
Line 382, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 4746327490 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 4746368305 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4746368305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test sysrst_ctrl_edge_detect has 3 failures.
12.sysrst_ctrl_edge_detect.104397548699996382156965841383206522899143563841654479467665329307357257423478
Line 406, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_edge_detect/latest/run.log
UVM_ERROR @ 3047776690 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 3047817505 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 3047817505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.sysrst_ctrl_edge_detect.53729823352743935175169784352017338826696767342522183074569731127973935617748
Line 382, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_edge_detect/latest/run.log
UVM_ERROR @ 2437906509 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 2437927342 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2437927342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
31.sysrst_ctrl_stress_all_with_rand_reset.53320344417880134512362960210999088170789266169601406777334690994599715394056
Line 405, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8010784342 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 8010871297 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 8010871297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_stress_all has 1 failures.
39.sysrst_ctrl_stress_all.88395325599992132048236133646566706504058788521968874315459596611111514088260
Line 389, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 317012582840 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 317012603673 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 317012603673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes has 8 failures:
Test sysrst_ctrl_combo_detect_ec_rst has 1 failures.
2.sysrst_ctrl_combo_detect_ec_rst.96368666320697931582775840766234813939521247473716954293736025276678682091636
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst/latest/run.log
Job timed out after 60 minutes
Test sysrst_ctrl_edge_detect has 1 failures.
7.sysrst_ctrl_edge_detect.42047831299757031428142025869575690569605776538136364284463445498337527280347
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_edge_detect/latest/run.log
Job timed out after 60 minutes
Test sysrst_ctrl_tl_errors has 1 failures.
8.sysrst_ctrl_tl_errors.3297954340266162145984876851107708051327716658499648821975994608648570394881
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_errors/latest/run.log
Job timed out after 60 minutes
Test sysrst_ctrl_intr_test has 1 failures.
8.sysrst_ctrl_intr_test.16452848538540536767700907467023785360132797994123400615365980599514247738850
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_intr_test/latest/run.log
Job timed out after 60 minutes
Test sysrst_ctrl_pin_override_test has 1 failures.
22.sysrst_ctrl_pin_override_test.32493586248823314800144339093852867498075611126389236687695822958745658539570
Log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_override_test/latest/run.log
Job timed out after 60 minutes
... and 2 more tests.
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 3 failures:
Test sysrst_ctrl_ultra_low_pwr has 2 failures.
0.sysrst_ctrl_ultra_low_pwr.45761352948167637424737305067842825781217185741187350939959656358705694120819
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 2404560543 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 2442060543 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
UVM_INFO @ 3317060543 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
UVM_INFO @ 4717060543 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 4730863510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
32.sysrst_ctrl_ultra_low_pwr.97955533077264280603822938081789065164427365815796531656775913484347985533015
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 2322194426 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 85184694426 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 85184694426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
17.sysrst_ctrl_stress_all_with_rand_reset.67219039819789954243900029929918927441327416810816282061843003951454562698043
Line 412, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7508152577 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 9120652577 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 9120652577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 2 failures:
27.sysrst_ctrl_combo_detect_with_pre_cond.8945950863571854158535722101183823282813210574345661926872154028953874021471
Line 398, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 25309617782 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 25309617782 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 25309617782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.sysrst_ctrl_combo_detect_with_pre_cond.13806938853764973581771114079872305291633676471752159665027574831963512583868
Line 435, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 63235267577 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 63235267577 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 63235267577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-* has 1 failures:
11.sysrst_ctrl_combo_detect_with_pre_cond.83187466095153125745914249433660672195705828435099090040921645840644345104008
Line 394, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 14739992458 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-4
UVM_INFO @ 14869992458 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 14889992458 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 25023903490 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x26
UVM_INFO @ 25024820153 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x1a
UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 1 failures:
35.sysrst_ctrl_ec_pwr_on_rst.37339186265480113962418046349154701483197750224014203549899517733702236471800
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
UVM_FATAL @ 2585181160 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
UVM_INFO @ 2585181160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---