USBDEV Simulation Results

Sunday September 21 2025 01:07:51 UTC

GitHub Revision: 1a5d173

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 22.239s 48 50 96.00
V1 csr_hw_reset usbdev_csr_hw_reset 19.969s 4 5 80.00
V1 csr_rw usbdev_csr_rw 18.022s 19 20 95.00
V1 csr_bit_bash usbdev_csr_bit_bash 3.590s 634.405us 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 2.310s 303.597us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 26.451s 18 20 90.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 18.022s 19 20 95.00
usbdev_csr_aliasing 2.310s 303.597us 5 5 100.00
V1 mem_walk usbdev_mem_walk 22.306s 4 5 80.00
V1 mem_partial_access usbdev_mem_partial_access 1.740s 175.682us 4 5 80.00
V1 TOTAL 107 115 93.04
V2 in_trans usbdev_in_trans 32.577s 47 50 94.00
V2 data_toggle_clear usbdev_data_toggle_clear 1.340s 605.280us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 20.271s 46 50 92.00
V2 av_buffer usbdev_av_buffer 26.885s 48 50 96.00
V2 rx_fifo usbdev_pkt_buffer 38.150s 23.225ms 48 50 96.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 0.880s 309.616us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0.750s 197.445us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 20.330s 48 50 96.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 0.840s 244.289us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 0.820s 244.233us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 0.780s 192.029us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 20.006s 48 50 96.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 17.882s 49 50 98.00
usbdev_stream_len_max 24.358s 47 50 94.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 26.431s 46 50 92.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 18.198s 48 50 96.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 24.174s 47 50 94.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 26.812s 48 50 96.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 22.287s 47 50 94.00
V2 out_stall usbdev_out_stall 15.963s 49 50 98.00
V2 in_stall usbdev_in_stall 22.435s 48 50 96.00
V2 out_iso usbdev_out_iso 28.239s 47 50 94.00
V2 in_iso usbdev_in_iso 18.260s 46 50 92.00
V2 pkt_received usbdev_pkt_received 15.655s 47 50 94.00
V2 pkt_sent usbdev_pkt_sent 0.830s 208.133us 49 50 98.00
V2 disconnected usbdev_disconnected 22.266s 48 50 96.00
V2 host_lost usbdev_host_lost 5.550s 4.156ms 1 1 100.00
V2 link_reset usbdev_link_reset 0.730s 209.409us 1 1 100.00
V2 link_suspend usbdev_link_suspend 16.290s 48 50 96.00
V2 link_resume usbdev_link_resume 32.950s 32.263ms 49 50 98.00
V2 av_empty usbdev_av_empty 0.770s 179.974us 5 5 100.00
V2 rx_full usbdev_rx_full 30.668s 47 50 94.00
V2 av_overflow usbdev_av_overflow 0.760s 145.407us 5 5 100.00
V2 link_in_err usbdev_link_in_err 22.293s 49 50 98.00
V2 rx_crc_err usbdev_rx_crc_err 20.745s 47 50 94.00
V2 rx_pid_err usbdev_rx_pid_err 0.770s 201.680us 4 5 80.00
V2 rx_bitstuff_err usbdev_bitstuff_err 21.966s 47 50 94.00
V2 link_out_err usbdev_link_out_err 1.220s 578.616us 1 1 100.00
V2 enable usbdev_enable 15.728s 48 50 96.00
V2 resume_link_active usbdev_resume_link_active 17.400s 20.174ms 20 20 100.00
V2 device_address usbdev_device_address 52.780s 49.841ms 48 50 96.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 1.110s 555.362us 1 1 100.00
V2 setup_stage usbdev_setup_stage 22.417s 48 50 96.00
V2 endpoint_access usbdev_endpoint_access 1.970s 1.049ms 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 24.009s 46 50 92.00
V2 endpoint_types usbdev_endpoint_types 24.465s 195 200 97.50
V2 out_trans_nak usbdev_out_trans_nak 22.512s 49 50 98.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 26.495s 46 50 92.00
V2 nak_trans usbdev_nak_trans 22.263s 48 50 96.00
V2 stall_trans usbdev_stall_trans 24.140s 45 50 90.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 0.800s 203.844us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 24.489s 47 50 94.00
V2 pending_in_trans usbdev_pending_in_trans 20.019s 47 50 94.00
V2 streaming_test usbdev_streaming_out 1.206m 4.078ms 47 50 94.00
V2 max_clock_error_untracked usbdev_freq_hiclk 1.997m 106.189ms 5 5 100.00
usbdev_freq_loclk 1.766m 120.086ms 4 5 80.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 1.885m 115.107ms 4 5 80.00
usbdev_freq_loclk_max 1.765m 107.897ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 2.023m 119.148ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 1.272m 4.473ms 47 50 94.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 1.244m 4.343ms 47 50 94.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 32.120s 7.703ms 48 50 96.00
V2 device_timeout usbdev_device_timeout 28.099s 46 50 92.00
V2 packet_buffer usbdev_pkt_buffer 38.150s 23.225ms 48 50 96.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 18.333s 0 1 0.00
V2 aon_wake_resume usbdev_aon_wake_resume 28.070s 29.695ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 22.498s 45 50 90.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 26.015s 47 50 94.00
V2 invalid_sync usbdev_invalid_sync 1.495m 4.985ms 47 50 94.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 1.172m 3.907ms 46 50 92.00
V2 low_speed_traffic usbdev_low_speed_traffic 1.547m 5.377ms 48 50 96.00
V2 rand_bus_resets usbdev_rand_bus_resets 2.005m 6.727ms 9 10 90.00
V2 rand_disconnects usbdev_rand_bus_disconnects 1.293m 5.313ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 1.980m 10.410ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 59.420s 3.320ms 23 25 92.00
usbdev_max_usb_traffic 59.590s 3.290ms 13 15 86.67
V2 stress_usb_traffic usbdev_stress_usb_traffic 1.187m 15.522ms 10 10 100.00
V2 in_packet_retraction usbdev_iso_retraction 1.555m 13.473ms 48 50 96.00
V2 data_toggle_restore usbdev_data_toggle_restore 18.268s 46 50 92.00
V2 setup_priority usbdev_setup_priority 1.040s 404.380us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 22.482s 47 50 94.00
V2 tx_rx_disruption usbdev_tx_rx_disruption 28.487s 476 500 95.20
V2 fifo_levels usbdev_fifo_levels 33.015s 158 160 98.75
V2 rxenable_out_conditional usbdev_rxenable_out 0.780s 156.715us 5 5 100.00
V2 intr_test usbdev_intr_test 24.195s 46 50 92.00
V2 alert_test usbdev_alert_test 20.401s 45 50 90.00
V2 tl_d_oob_addr_access usbdev_tl_errors 22.479s 18 20 90.00
V2 tl_d_illegal_access usbdev_tl_errors 22.479s 18 20 90.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 19.969s 4 5 80.00
usbdev_csr_rw 18.022s 19 20 95.00
usbdev_csr_aliasing 2.310s 303.597us 5 5 100.00
usbdev_same_csr_outstanding 15.942s 19 20 95.00
V2 tl_d_partial_access usbdev_csr_hw_reset 19.969s 4 5 80.00
usbdev_csr_rw 18.022s 19 20 95.00
usbdev_csr_aliasing 2.310s 303.597us 5 5 100.00
usbdev_same_csr_outstanding 15.942s 19 20 95.00
V2 TOTAL 3586 3769 95.14
V2S tl_intg_err usbdev_sec_cm 1.250s 863.822us 5 5 100.00
usbdev_tl_intg_err 24.365s 18 20 90.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 24.365s 18 20 90.00
V2S TOTAL 23 25 92.00
V3 dpi_config_host usbdev_dpi_config_host 22.850s 5.107ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 0.600s 54.262us 0 10 0.00
usbdev_stress_all 32.409s 0 50 0.00
TOTAL 3717 3970 93.63

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.06 98.80 95.55 97.23 94.92 98.34 95.94 98.64

Failure Buckets