CHIP Simulation Results

Sunday September 21 2025 01:07:51 UTC

GitHub Revision: `1a5d173`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.673m	2.718ms	1	3	33.33
		chip_sw_example_rom	1.011m	2.306ms	1	3	33.33
		chip_sw_example_manufacturer	1.139m	2.710ms	1	3	33.33
		chip_sw_example_concurrency	1.962m	2.727ms	1	3	33.33
V1	csr_hw_reset	chip_csr_hw_reset			0	5	0.00
V1	csr_rw	chip_csr_rw			0	20	0.00
V1	csr_bit_bash	chip_csr_bit_bash			0	5	0.00
V1	csr_aliasing	chip_csr_aliasing			0	5	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset			0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing			0	5	0.00
		chip_csr_rw			0	20	0.00
V1	xbar_smoke	xbar_smoke	59.492s		91	100	91.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.541m	4.285ms	1	3	33.33
V1	chip_sw_gpio_in	chip_sw_gpio	4.541m	4.285ms	1	3	33.33
V1	chip_sw_gpio_irq	chip_sw_gpio	4.541m	4.285ms	1	3	33.33
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.528m	4.752ms	3	5	60.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.528m	4.752ms	3	5	60.00
		chip_sw_uart_tx_rx_idx1	5.801m	4.755ms	3	5	60.00
		chip_sw_uart_tx_rx_idx2	6.283m	4.919ms	3	5	60.00
		chip_sw_uart_tx_rx_idx3	5.385m	3.755ms	1	5	20.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	28.672m	13.710ms	16	20	80.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	29.268m	13.543ms	2	5	40.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	17.043m	13.644ms	3	5	60.00
V1		TOTAL			127	220	57.73
V2	chip_pin_mux	chip_padctrl_attributes			0	10	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes			0	10	0.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.109m	3.120ms	1	3	33.33
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.372m	6.004ms	1	3	33.33
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.655m	4.180ms	1	3	33.33
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	17.945m	16.847ms	2	5	40.00
		chip_tap_straps_testunlock0	6.728m	6.997ms	3	5	60.00
		chip_tap_straps_rma	2.455m	3.980ms	3	5	60.00
		chip_tap_straps_prod	14.160m	13.898ms	3	5	60.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	1.939m	2.495ms	1	3	33.33
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.491m	9.021ms	1	3	33.33
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.692m	4.265ms	3	6	50.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.692m	4.265ms	3	6	50.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.550m	7.708ms	1	3	33.33
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	36.207m	19.937ms	0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.960m	4.638ms	1	3	33.33
		chip_sw_flash_ctrl_access_jitter_en	8.019m	5.794ms	1	3	33.33
		chip_sw_otbn_ecdsa_op_irq_jitter_en	29.027s		0	3	0.00
		chip_sw_aes_enc_jitter_en	29.679s		0	3	0.00
		chip_sw_edn_entropy_reqs_jitter	7.654m	5.573ms	1	3	33.33
		chip_sw_hmac_enc_jitter_en	36.703s		0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en	22.540m	10.607ms	1	3	33.33
		chip_sw_kmac_mode_kmac_jitter_en	2.642m	3.384ms	1	3	33.33
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.730m	4.907ms	1	3	33.33
		chip_sw_clkmgr_jitter	2.212m	2.321ms	1	3	33.33
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	15.291s		0	1	0.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.102m	5.803ms	2	5	40.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	39.088s		0	3	0.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.892m	2.267ms	1	3	33.33
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	39.088s		0	3	0.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	7.500m		1	3	33.33
		chip_sw_aes_smoketest	2.674m	2.999ms	1	3	33.33
		chip_sw_aon_timer_smoketest	3.028m	3.205ms	1	3	33.33
		chip_sw_clkmgr_smoketest	2.212m	2.919ms	2	3	66.67
		chip_sw_csrng_smoketest	2.438m	2.269ms	2	3	66.67
		chip_sw_entropy_src_smoketest	13.307m	6.524ms	2	3	66.67
		chip_sw_gpio_smoketest	3.006m	3.418ms	2	3	66.67
		chip_sw_hmac_smoketest	2.496m	3.038ms	2	3	66.67
		chip_sw_kmac_smoketest	5.033m		1	3	33.33
		chip_sw_otbn_smoketest	16.237m	7.594ms	1	3	33.33
		chip_sw_pwrmgr_smoketest	2.736m	5.712ms	1	3	33.33
		chip_sw_pwrmgr_usbdev_smoketest	4.495m	6.572ms	2	3	66.67
		chip_sw_rv_plic_smoketest	7.083m		1	3	33.33
		chip_sw_rv_timer_smoketest	2.223m	3.215ms	1	3	33.33
		chip_sw_rstmgr_smoketest	2.290m	2.558ms	1	3	33.33
		chip_sw_sram_ctrl_smoketest	2.217m	2.676ms	2	3	66.67
		chip_sw_uart_smoketest	2.441m	3.515ms	2	3	66.67
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.407m	2.676ms	1	3	33.33
V2	chip_sw_rom_functests	rom_keymgr_functest	6.447m	5.727ms	2	3	66.67
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.036h	60.730ms	1	3	33.33
V2	chip_sw_secure_boot	rom_e2e_smoke	46.331m	16.199ms	2	3	66.67
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.800m		0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	39.868s		0	3	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.873m	3.759ms	0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.880h	53.832ms	1	3	33.33
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.128h	56.700ms	1	3	33.33
V2	tl_d_oob_addr_access	chip_tl_errors			0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors			0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding			0	20	0.00
		chip_csr_hw_reset			0	5	0.00
		chip_csr_rw			0	20	0.00
V2	tl_d_partial_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding			0	20	0.00
		chip_csr_hw_reset			0	5	0.00
		chip_csr_rw			0	20	0.00
V2	xbar_base_random_sequence	xbar_random	52.020s	2.374ms	83	100	83.00
V2	xbar_random_delay	xbar_smoke_zero_delays	44.722s		91	100	91.00
		xbar_smoke_large_delays	1.183m	8.462ms	88	100	88.00
		xbar_smoke_slow_rsp	1.503m	6.355ms	86	100	86.00
		xbar_random_zero_delays	43.868s		91	100	91.00
		xbar_random_large_delays	6.062m	60.354ms	88	100	88.00
		xbar_random_slow_rsp	4.893m	33.682ms	88	100	88.00
V2	xbar_unmapped_address	xbar_unmapped_addr	35.050s	1.249ms	89	100	89.00
		xbar_error_and_unmapped_addr	38.310s	1.470ms	93	100	93.00
V2	xbar_error_cases	xbar_error_random	49.875s		88	100	88.00
		xbar_error_and_unmapped_addr	38.310s	1.470ms	93	100	93.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.266m	3.429ms	90	100	90.00
		xbar_access_same_device_slow_rsp	12.125m	88.968ms	89	100	89.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	50.730s	2.418ms	90	100	90.00
V2	xbar_stress_all	xbar_stress_all	5.824m	15.991ms	86	100	86.00
		xbar_stress_all_with_error	5.424m	18.756ms	85	100	85.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	7.557m	13.988ms	89	100	89.00
		xbar_stress_all_with_reset_error	7.711m	19.172ms	93	100	93.00
V2	rom_e2e_smoke	rom_e2e_smoke	46.331m	16.199ms	2	3	66.67
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	42.625m	30.547ms	2	3	66.67
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	48.784m	16.188ms	2	3	66.67
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	12.302s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	9.749s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	9.793s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	9.889s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	21.027s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	21.739s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	22.586s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	21.801s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	29.007s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	36.512s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	23.056s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	24.193s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	22.702s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	21.246s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	21.599s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	23.632s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	21.770s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	21.597s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	21.232s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	20.742s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	22.834s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	32.132s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	19.599s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	20.137s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	22.635s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	21.795s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	22.923s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	19.306s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	22.038s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	21.707s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	3.407m		0	3	0.00
		rom_e2e_asm_init_dev	3.712m		0	3	0.00
		rom_e2e_asm_init_prod	2.649m		0	3	0.00
		rom_e2e_asm_init_prod_end	3.110m		0	3	0.00
		rom_e2e_asm_init_rma	6.253m		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	48.735m	16.452ms	2	3	66.67
		rom_e2e_keymgr_init_rom_ext_no_meas	47.411m	15.087ms	2	3	66.67
		rom_e2e_keymgr_init_rom_ext_invalid_meas	48.315m	15.100ms	2	3	66.67
V2	rom_e2e_static_critical	rom_e2e_static_critical	48.730m	15.724ms	1	3	33.33
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	43.937m	34.747ms	0	3	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	43.937m	34.747ms	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.517m	3.438ms	1	3	33.33
		chip_sw_aes_enc_jitter_en	29.679s		0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	1.823m	2.219ms	1	3	33.33
V2	chip_sw_aes_idle	chip_sw_aes_idle	1.982m	3.075ms	1	3	33.33
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	21.926s		0	3	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.679m	2.890ms	0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.184m	5.607ms	1	3	33.33
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	7.566m	5.522ms	78	100	78.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	7.575m	5.060ms	1	3	33.33
		chip_plic_all_irqs_10	3.234m	3.055ms	1	3	33.33
		chip_plic_all_irqs_20	5.458m	4.089ms	1	3	33.33
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.460m	3.279ms	1	3	33.33
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	17.951m	12.888ms	1	3	33.33
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	36.667s		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	3.099m	2.840ms	0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	13.652s		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	16.394m	8.577ms	1	3	33.33
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	17.717m	8.947ms	1	3	33.33
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.646m	7.876ms	1	3	33.33
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	14.141s		0	3	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.220m	3.801ms	1	3	33.33
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	2.736m	5.712ms	1	3	33.33
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.220m	3.801ms	1	3	33.33
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.862m	9.269ms	1	3	33.33
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.862m	9.269ms	1	3	33.33
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.950m	6.334ms	3	5	60.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	14.759s		0	3	0.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	40.758s		0	3	0.00
		chip_sw_aes_idle	1.982m	3.075ms	1	3	33.33
		chip_sw_hmac_enc_idle	40.771s		0	3	0.00
		chip_sw_kmac_idle	1.442m	2.302ms	1	3	33.33
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.024m	4.647ms	1	3	33.33
		chip_sw_clkmgr_off_hmac_trans	4.534m	4.824ms	1	3	33.33
		chip_sw_clkmgr_off_kmac_trans	3.469m	4.765ms	1	3	33.33
		chip_sw_clkmgr_off_otbn_trans	2.926m	4.883ms	1	3	33.33
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.162m	10.536ms	1	3	33.33
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	42.576s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.759m	4.683ms	1	3	33.33
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	43.363s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.111m	4.503ms	1	3	33.33
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.090m	3.845ms	1	3	33.33
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.058m	5.179ms	1	3	33.33
		chip_sw_ast_clk_outputs	8.550m	7.708ms	1	3	33.33
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.796m	5.694ms	1	3	33.33
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	43.363s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.111m	4.503ms	1	3	33.33
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.960m	4.638ms	1	3	33.33
		chip_sw_flash_ctrl_access_jitter_en	8.019m	5.794ms	1	3	33.33
		chip_sw_otbn_ecdsa_op_irq_jitter_en	29.027s		0	3	0.00
		chip_sw_aes_enc_jitter_en	29.679s		0	3	0.00
		chip_sw_edn_entropy_reqs_jitter	7.654m	5.573ms	1	3	33.33
		chip_sw_hmac_enc_jitter_en	36.703s		0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en	22.540m	10.607ms	1	3	33.33
		chip_sw_kmac_mode_kmac_jitter_en	2.642m	3.384ms	1	3	33.33
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.730m	4.907ms	1	3	33.33
		chip_sw_clkmgr_jitter	2.212m	2.321ms	1	3	33.33
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	49.738s		0	3	0.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.311m	5.041ms	1	3	33.33
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	39.168s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	57.456m	24.945ms	1	3	33.33
		chip_sw_aes_enc_jitter_en_reduced_freq	2.572m	3.144ms	1	3	33.33
		chip_sw_hmac_enc_jitter_en_reduced_freq	1.977m	3.269ms	1	3	33.33
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	38.299s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.965m	3.273ms	1	3	33.33
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	6.267m	5.226ms	1	3	33.33
		chip_sw_flash_init_reduced_freq	22.586m	22.386ms	1	3	33.33
		chip_sw_csrng_edn_concurrency_reduced_freq	33.602s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.550m	7.708ms	1	3	33.33
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	56.411s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	27.807s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	7.566m	5.522ms	78	100	78.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	16.394m	8.577ms	1	3	33.33
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.125m	7.165ms	1	3	33.33
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	4.121m	4.632ms	1	3	33.33
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.402m	7.210ms	1	3	33.33
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.712m	2.571ms	1	3	33.33
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.043h	27.264ms	4	10	40.00
		chip_sw_entropy_src_ast_rng_req	13.514s		0	3	0.00
		chip_sw_edn_entropy_reqs	7.538m	5.611ms	1	3	33.33
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	13.514s		0	3	0.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.125m	7.165ms	1	3	33.33
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.480m	2.263ms	1	3	33.33
V2	chip_sw_flash_init	chip_sw_flash_init	24.451m	24.890ms	1	3	33.33
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.283m	5.712ms	1	3	33.33
		chip_sw_flash_ctrl_access_jitter_en	8.019m	5.794ms	1	3	33.33
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.770m	4.253ms	1	3	33.33
		chip_sw_flash_ctrl_ops_jitter_en	5.960m	4.638ms	1	3	33.33
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	59.123m	43.039ms	1	3	33.33
V2	chip_sw_flash_scramble	chip_sw_flash_init	24.451m	24.890ms	1	3	33.33
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.610m	3.319ms	1	3	33.33
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	13.971m	8.544ms	1	3	33.33
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.151m	4.629ms	1	3	33.33
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	59.123m	43.039ms	1	3	33.33
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.151m	4.629ms	1	3	33.33
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.151m	4.629ms	1	3	33.33
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.151m	4.629ms	1	3	33.33
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.151m	4.629ms	1	3	33.33
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	7.566m	5.522ms	78	100	78.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access			0	3	0.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.603m	5.090ms	1	3	33.33
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	27.001s		0	3	0.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	27.001s		0	3	0.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	1.668m	2.555ms	1	3	33.33
		chip_sw_hmac_enc_jitter_en	36.703s		0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	40.771s		0	3	0.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.579m	3.079ms	0	3	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	4.482m	3.251ms	1	3	33.33
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.635m	5.610ms	1	3	33.33
		chip_sw_i2c_host_tx_rx_idx1	16.697s		0	3	0.00
		chip_sw_i2c_host_tx_rx_idx2	31.999s		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.635m	3.194ms	1	3	33.33
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	13.971m	8.544ms	1	3	33.33
		chip_sw_keymgr_key_derivation_jitter_en	22.540m	10.607ms	1	3	33.33
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	17.507m	9.236ms	1	3	33.33
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	21.926s		0	3	0.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	30.788m	11.425ms	1	3	33.33
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	1.773m	2.342ms	1	3	33.33
		chip_sw_kmac_mode_kmac	2.738m	3.330ms	1	3	33.33
		chip_sw_kmac_mode_kmac_jitter_en	2.642m	3.384ms	1	3	33.33
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	13.971m	8.544ms	1	3	33.33
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	11.846m	13.435ms	12	15	80.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.143m	2.873ms	1	3	33.33
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	13.064m	7.193ms	1	3	33.33
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.442m	2.302ms	1	3	33.33
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.184m	5.607ms	1	3	33.33
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	17.945m	16.847ms	2	5	40.00
		chip_tap_straps_rma	2.455m	3.980ms	3	5	60.00
		chip_tap_straps_prod	14.160m	13.898ms	3	5	60.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	28.889s		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	11.846m	13.435ms	12	15	80.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	11.846m	13.435ms	12	15	80.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	11.846m	13.435ms	12	15	80.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	15.849m	8.647ms	1	3	33.33
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.151m	4.629ms	1	3	33.33
		chip_sw_flash_rma_unlocked	59.123m	43.039ms	1	3	33.33
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	37.965s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.415s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	8.094m	7.555ms	1	3	33.33
		chip_sw_otp_ctrl_lc_signals_rma	6.362m	5.302ms	1	3	33.33
		chip_sw_lc_ctrl_transition	11.846m	13.435ms	12	15	80.00
		chip_sw_keymgr_key_derivation	13.971m	8.544ms	1	3	33.33
		chip_sw_rom_ctrl_integrity_check	4.331m	9.612ms	1	3	33.33
		chip_sw_sram_ctrl_execution_main	5.346m	7.012ms	1	3	33.33
		chip_prim_tl_access			0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.796m	5.694ms	1	3	33.33
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	42.576s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.759m	4.683ms	1	3	33.33
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	43.363s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.111m	4.503ms	1	3	33.33
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.090m	3.845ms	1	3	33.33
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.058m	5.179ms	1	3	33.33
		chip_tap_straps_dev	17.945m	16.847ms	2	5	40.00
		chip_tap_straps_rma	2.455m	3.980ms	3	5	60.00
		chip_tap_straps_prod	14.160m	13.898ms	3	5	60.00
		chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	14.469s		0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	15.093s		0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	14.540s		0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	2.757m	3.940ms	1	3	33.33
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	17.360m	28.223ms	1	3	33.33
		chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	56.890m	49.583ms	1	3	33.33
		chip_sw_lc_walkthrough_prod	1.014h	46.620ms	1	3	33.33
		chip_sw_lc_walkthrough_prodend	8.066m	9.669ms	1	3	33.33
		chip_sw_lc_walkthrough_rma	14.225s		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	17.360m	28.223ms	1	3	33.33
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.074m	2.740ms	1	3	33.33
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.050m	2.943ms	1	3	33.33
		rom_volatile_raw_unlock	4.547m		0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	54.171m	16.394ms	1	3	33.33
		chip_sw_otbn_ecdsa_op_irq_jitter_en	29.027s		0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	40.758s		0	3	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	40.758s		0	3	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	40.758s		0	3	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	39.440s		0	3	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	11.846m	13.435ms	12	15	80.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	24.451m	24.890ms	1	3	33.33
		chip_sw_otbn_mem_scramble	39.440s		0	3	0.00
		chip_sw_keymgr_key_derivation	13.971m	8.544ms	1	3	33.33
		chip_sw_sram_ctrl_scrambled_access	5.173m	4.288ms	1	3	33.33
		chip_sw_rv_core_ibex_icache_invalidate	2.547m	2.758ms	1	3	33.33
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	24.451m	24.890ms	1	3	33.33
		chip_sw_otbn_mem_scramble	39.440s		0	3	0.00
		chip_sw_keymgr_key_derivation	13.971m	8.544ms	1	3	33.33
		chip_sw_sram_ctrl_scrambled_access	5.173m	4.288ms	1	3	33.33
		chip_sw_rv_core_ibex_icache_invalidate	2.547m	2.758ms	1	3	33.33
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	11.846m	13.435ms	12	15	80.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.817m	4.995ms	1	3	33.33
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	28.889s		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	37.965s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.415s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	8.094m	7.555ms	1	3	33.33
		chip_sw_otp_ctrl_lc_signals_rma	6.362m	5.302ms	1	3	33.33
		chip_sw_lc_ctrl_transition	11.846m	13.435ms	12	15	80.00
		chip_prim_tl_access			0	3	0.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access			0	3	0.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	14.559s		0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.051m	8.351ms	1	3	33.33
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	21.979m	27.512ms	1	3	33.33
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	42.496s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	7.253m	9.863ms	1	3	33.33
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.670m	6.268ms	1	3	33.33
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	20.837m	25.095ms	1	3	33.33
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	11.637m	14.157ms	1	3	33.33
		chip_sw_aon_timer_wdog_bite_reset	6.862m	9.269ms	1	3	33.33
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	9.779m	9.780ms	1	3	33.33
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.486m	4.607ms	1	3	33.33
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.051m	8.351ms	1	3	33.33
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	2.831m	3.684ms	1	3	33.33
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	34.622s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.931m	7.062ms	1	3	33.33
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.954m	5.666ms	1	3	33.33
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	23.263m	22.087ms	1	3	33.33
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.858m	8.821ms	1	3	33.33
		chip_sw_pwrmgr_all_reset_reqs	14.046m	12.011ms	1	3	33.33
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	24.340m	25.958ms	1	3	33.33
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	31.519s		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	7.566m	5.522ms	78	100	78.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.331m	9.612ms	1	3	33.33
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.331m	9.612ms	1	3	33.33
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.046m	12.011ms	1	3	33.33
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	23.263m	22.087ms	1	3	33.33
		chip_sw_pwrmgr_wdog_reset	4.486m	4.607ms	1	3	33.33
		chip_sw_pwrmgr_smoketest	2.736m	5.712ms	1	3	33.33
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.340m	4.536ms	1	3	33.33
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.081m	4.493ms	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.325m	4.632ms	1	3	33.33
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	17.951m	12.888ms	1	3	33.33
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.771m	2.280ms	1	3	33.33
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	7.566m	5.522ms	78	100	78.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	17.717m	8.947ms	1	3	33.33
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.098m	4.491ms	1	3	33.33
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.844m	4.910ms	1	3	33.33
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.618m	2.777ms	1	3	33.33
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.547m	2.758ms	1	3	33.33
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.081m	4.493ms	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.081m	4.493ms	0	3	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	12.934m	12.662ms	1	3	33.33
V2	chip_jtag_mem_access	chip_jtag_mem_access	15.017m	13.381ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.340m	4.536ms	1	3	33.33
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	41.743s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	43.786s		0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	2.455m	3.980ms	3	5	60.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	7.575m	5.060ms	1	3	33.33
		chip_plic_all_irqs_10	3.234m	3.055ms	1	3	33.33
		chip_plic_all_irqs_20	5.458m	4.089ms	1	3	33.33
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.760m	2.971ms	1	3	33.33
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.434m	2.870ms	1	3	33.33
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	46.331m	16.199ms	2	3	66.67
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	5.919m	6.447ms	1	3	33.33
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.947m	3.503ms	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	14.378s		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.225m	3.218ms	1	3	33.33
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.173m	4.288ms	1	3	33.33
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.730m	4.907ms	1	3	33.33
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.193m	9.117ms	1	3	33.33
		chip_sw_sleep_sram_ret_contents_scramble	7.324m	7.427ms	1	3	33.33
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	5.346m	7.012ms	1	3	33.33
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	7.566m	5.522ms	78	100	78.00
		chip_sw_data_integrity_escalation	5.692m	4.265ms	3	6	50.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.858m	8.821ms	1	3	33.33
		chip_sw_sysrst_ctrl_reset	15.588m	22.407ms	1	3	33.33
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	16.631s		0	3	0.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.649m	4.449ms	1	3	33.33
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.194m	5.153ms	1	3	33.33
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	15.588m	22.407ms	1	3	33.33
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	15.588m	22.407ms	1	3	33.33
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	37.927m	20.034ms	1	3	33.33
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	37.927m	20.034ms	1	3	33.33
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.978m	5.751ms	1	3	33.33
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	43.937m	34.747ms	0	3	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	14.177s		0	1	0.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	13.341s		0	1	0.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	12.758s		0	1	0.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	11.770s		0	1	0.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	11.100s		0	1	0.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	9.698s		0	1	0.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	13.555s		0	1	0.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	9.874s		0	1	0.00
V2		TOTAL			1786	2657	67.22
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.127m	2.745ms	1	3	33.33
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.445m	2.955ms	1	3	33.33
V2S		TOTAL			2	6	33.33
V3	chip_sw_coremark	chip_sw_coremark	14.387s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	29.244s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.968s		0	1	0.00
		rom_e2e_jtag_debug_dev	18.507s		0	1	0.00
		rom_e2e_jtag_debug_rma	28.204s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	13.616s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.656s		0	1	0.00
		rom_e2e_jtag_inject_rma	15.185s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	3.436m		0	3	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.740m	4.857ms	1	3	33.33
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.416m	2.605ms	1	3	33.33
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	7.547m	3.671ms	1	3	33.33
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	24.378m	10.521ms	1	3	33.33
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.125m	2.555ms	1	3	33.33
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.493m	5.071ms	2	3	66.67
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	48.670s	2.302ms	1	3	33.33
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	14.478s		0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.815m	5.932ms	1	3	33.33
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	41.806s		0	3	0.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.046m	12.011ms	1	3	33.33
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.968s		0	1	0.00
		rom_e2e_jtag_debug_dev	18.507s		0	1	0.00
		rom_e2e_jtag_debug_rma	28.204s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.718m	5.553ms	1	3	33.33
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	7.566m	5.522ms	78	100	78.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.537h	38.447ms	1	3	33.33
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.537h	38.447ms	1	3	33.33
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.958m	3.605ms	1	3	33.33
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.528m	4.752ms	3	5	60.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	9.641s		0	1	0.00
V3		TOTAL			12	51	23.53
	Unmapped tests	chip_sival_flash_info_access	2.011m	3.150ms	1	3	33.33
		chip_sw_rstmgr_rst_cnsty_escalation	5.376m	4.715ms	1	3	33.33
		chip_sw_otp_ctrl_ecc_error_vendor_test	1.683m	2.095ms	1	3	33.33
		chip_sw_otp_ctrl_descrambling	2.700m	3.574ms	1	3	33.33
		chip_sw_pwrmgr_lowpower_cancel	2.832m	3.589ms	1	3	33.33
		chip_sw_pwrmgr_sleep_wake_5_bug	17.466s		0	3	0.00
		chip_sw_flash_ctrl_write_clear	3.117m	2.892ms	1	3	33.33
		TOTAL			1933	2955	65.41

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
86.20	85.27	82.55	88.45	--	88.86	74.09	97.99

Failure Buckets

Job returned non-zero exit code has 773 failures:

Test cover_reg_top has 1 failures.

cover_reg_top
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/cover_reg_top/build.log

  recompiling module tb
  All of 675 modules done
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.

  Please contact VCS Customer Support at 1-800-VERILOG for more information.

  CPU time: 169.337 seconds to compile
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1

Test chip_sw_example_flash has 2 failures.

0.chip_sw_example_flash.55357701195165501636765927618213324954125399271290585824376864507829996025921
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_flash/latest/run.log

    <builtin>: in <toplevel>
  Repository rule http_archive defined at:
    /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'rules_rust+':
     Traceback (most recent call last):
      File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/rules_rust/releases/download/0.59.2/rules_rust-0.59.2.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust+/temp12335731897591490049/rules_rust-0.59.2.tar.gz: Unknown host: github.com
  ERROR: @rules_rust//rust/toolchain/channel :: Error loading option @rules_rust//rust/toolchain/channel: java.io.IOException: Error downloading [https://github.com/bazelbuild/rules_rust/releases/download/0.59.2/rules_rust-0.59.2.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust+/temp12335731897591490049/rules_rust-0.59.2.tar.gz: Unknown host: github.com
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 2

1.chip_sw_example_flash.40981524474276481698250771500332947008533024773046373882373894576070780420295
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_flash/latest/run.log

      File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/lowrisc-toolchains/releases/download/20240923-1/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain/temp9972728995775135721/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz: Unknown host: github.com
  ERROR: no such package '@@+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain//': java.io.IOException: Error downloading [https://github.com/lowRISC/lowrisc-toolchains/releases/download/20240923-1/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain/temp9972728995775135721/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz: Unknown host: github.com
  ERROR: /nightly/current_run/opentitan/toolchain/BUILD:215:8: //toolchain:system_includes depends on @@+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain//:lib-clang-include in repository @@+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain which failed to fetch. no such package '@@+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain//': java.io.IOException: Error downloading [https://github.com/lowRISC/lowrisc-toolchains/releases/download/20240923-1/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain/temp9972728995775135721/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz: Unknown host: github.com
  ERROR: Analysis of target '//sw/device/tests:example_test_from_flash_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 1.588s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_rom has 2 failures.

0.chip_sw_example_rom.17135575898149328500601522602208458450461935645918204518510551302840103206530
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

    <builtin>: in <toplevel>
  Repository rule http_archive defined at:
    /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'rules_rust+':
     Traceback (most recent call last):
      File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/rules_rust/releases/download/0.59.2/rules_rust-0.59.2.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust+/temp6054425855398821463/rules_rust-0.59.2.tar.gz: Unknown host: github.com
  ERROR: @rules_rust//rust/toolchain/channel :: Error loading option @rules_rust//rust/toolchain/channel: java.io.IOException: Error downloading [https://github.com/bazelbuild/rules_rust/releases/download/0.59.2/rules_rust-0.59.2.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust+/temp6054425855398821463/rules_rust-0.59.2.tar.gz: Unknown host: github.com
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 2

1.chip_sw_example_rom.70720324581281884068242083463444649773958005788235498661294824516291039963564
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log

      File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/lowrisc-toolchains/releases/download/20240923-1/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain/temp182423340764511857/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz: Unknown host: github.com
  ERROR: no such package '@@+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain//': java.io.IOException: Error downloading [https://github.com/lowRISC/lowrisc-toolchains/releases/download/20240923-1/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain/temp182423340764511857/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz: Unknown host: github.com
  ERROR: /nightly/current_run/opentitan/toolchain/BUILD:215:8: //toolchain:system_includes depends on @@+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain//:lib-clang-include in repository @@+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain which failed to fetch. no such package '@@+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain//': java.io.IOException: Error downloading [https://github.com/lowRISC/lowrisc-toolchains/releases/download/20240923-1/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain/temp182423340764511857/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz: Unknown host: github.com
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 1.570s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 2 failures.

0.chip_sw_example_manufacturer.89287099194417453640595585812904256152861085147853159918330454832017685457305
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

    <builtin>: in <toplevel>
  Repository rule http_archive defined at:
    /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'rules_rust+':
     Traceback (most recent call last):
      File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/rules_rust/releases/download/0.59.2/rules_rust-0.59.2.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust+/temp2522264174702770436/rules_rust-0.59.2.tar.gz: Unknown host: github.com
  ERROR: @rules_rust//rust/toolchain/channel :: Error loading option @rules_rust//rust/toolchain/channel: java.io.IOException: Error downloading [https://github.com/bazelbuild/rules_rust/releases/download/0.59.2/rules_rust-0.59.2.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust+/temp2522264174702770436/rules_rust-0.59.2.tar.gz: Unknown host: github.com
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 2

1.chip_sw_example_manufacturer.46722166523898518484714116726696096672977175015062297001901564188238959682622
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log

      File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/lowrisc-toolchains/releases/download/20240923-1/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain/temp6762616013911480163/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz: Unknown host: github.com
  ERROR: no such package '@@+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain//': java.io.IOException: Error downloading [https://github.com/lowRISC/lowrisc-toolchains/releases/download/20240923-1/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain/temp6762616013911480163/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz: Unknown host: github.com
  ERROR: /nightly/current_run/opentitan/toolchain/BUILD:215:8: //toolchain:system_includes depends on @@+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain//:lib-clang-include in repository @@+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain which failed to fetch. no such package '@@+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain//': java.io.IOException: Error downloading [https://github.com/lowRISC/lowrisc-toolchains/releases/download/20240923-1/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain/temp6762616013911480163/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz: Unknown host: github.com
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 0.596s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_concurrency has 2 failures.

0.chip_sw_example_concurrency.21895545642767764612913273156693256798813613369511793884414996662445471428471
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log

    <builtin>: in <toplevel>
  Repository rule http_archive defined at:
    /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'rules_rust+':
     Traceback (most recent call last):
      File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/rules_rust/releases/download/0.59.2/rules_rust-0.59.2.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust+/temp7033857820671665982/rules_rust-0.59.2.tar.gz: Unknown host: github.com
  ERROR: @rules_rust//rust/toolchain/channel :: Error loading option @rules_rust//rust/toolchain/channel: java.io.IOException: Error downloading [https://github.com/bazelbuild/rules_rust/releases/download/0.59.2/rules_rust-0.59.2.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust+/temp7033857820671665982/rules_rust-0.59.2.tar.gz: Unknown host: github.com
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 2

1.chip_sw_example_concurrency.115228437394790218307008264080124263672287983270862769228774374406565953912277
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_concurrency/latest/run.log

      File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/lowrisc-toolchains/releases/download/20240923-1/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain/temp11944528940737691725/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz: Unknown host: github.com
  ERROR: no such package '@@+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain//': java.io.IOException: Error downloading [https://github.com/lowRISC/lowrisc-toolchains/releases/download/20240923-1/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain/temp11944528940737691725/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz: Unknown host: github.com
  ERROR: /nightly/current_run/opentitan/toolchain/BUILD:215:8: //toolchain:system_includes depends on @@+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain//:lib-clang-include in repository @@+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain which failed to fetch. no such package '@@+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain//': java.io.IOException: Error downloading [https://github.com/lowRISC/lowrisc-toolchains/releases/download/20240923-1/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain/temp11944528940737691725/lowrisc-toolchain-rv32imcb-20240923-1.tar.xz: Unknown host: github.com
  ERROR: Analysis of target '//sw/device/tests:example_concurrency_test_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 1.966s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 310 more tests.

Job killed most likely because its dependent job failed. has 121 failures:
- Test chip_csr_bit_bash has 5 failures.
  - 0.chip_csr_bit_bash.68505794437396405801429922236874411653355283834167680551122412571981181535347
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
  - 1.chip_csr_bit_bash.7984202095303306085953466908723388577016251022858181481515011804784508332818
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log
  - ... and 3 more failures.
- Test chip_csr_aliasing has 5 failures.
  - 0.chip_csr_aliasing.92648766525986014598760064724976984542509314872840830580110708558942497078076
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
  - 1.chip_csr_aliasing.37506498622828398254465077292570323932769119511973485310810370549937090858633
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
  - ... and 3 more failures.
- Test chip_same_csr_outstanding has 20 failures.
  - 0.chip_same_csr_outstanding.6435515248124610068484039898633151945689856269107708680364594083867338694596
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
  - 1.chip_same_csr_outstanding.14360538415577107553197353239481781816042628739203589154440194044837230694334
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
  - ... and 18 more failures.
- Test chip_tl_errors has 30 failures.
  - 0.chip_tl_errors.26062532394186900025125401016415315723059865051211917716294555969568849597205
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log
  - 1.chip_tl_errors.88848245846436076668580718634883603468314443508391848098801822949682506931002
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_tl_errors/latest/run.log
  - ... and 28 more failures.
- Test chip_prim_tl_access has 3 failures.
  - 0.chip_prim_tl_access.18097787469653329118155722171710642445090204227376613936505187232909573526261
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log
  - 1.chip_prim_tl_access.88515149617183654408685597463308532890866146408447384399663844183336491615790
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_prim_tl_access/latest/run.log
  - ... and 1 more failures.
- ... and 5 more tests.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 74 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 74 failures.
  - 2.chip_sw_alert_handler_lpg_sleep_mode_alerts.46459252973157354775497335660260111834201488496613352106953161849509906261123
    Line 388, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3023.120940 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3023.120940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.chip_sw_alert_handler_lpg_sleep_mode_alerts.29240709030873288923107214584643598949402959210398652382679238033626158262875
    Line 403, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2679.433450 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2679.433450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 72 more failures.
Job timed out after * minutes has 43 failures:
- Test pad_ctrl_test_mode has 1 failures.
  - pad_ctrl_test_mode
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/build.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_aes_smoketest has 1 failures.
  - 1.chip_sw_aes_smoketest.63257251417095953763049382451851122410645579879387599433103396688768663070878
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_smoketest/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_rstmgr_smoketest has 1 failures.
  - 1.chip_sw_rstmgr_smoketest.10672801026010453239626694442589781519623520851390441229197826583798327132998
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_smoketest/latest/run.log
```
  Job timed out after 60 minutes
```
- Test xbar_random has 3 failures.
  - 1.xbar_random.51042659762376773728544391531791375992463716527620631475551504585484624788602
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.xbar_random/latest/run.log
```
  Job timed out after 60 minutes
```
  - 18.xbar_random.109667872801225287052601272175935993409676305391829027795858125666252880212677
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/18.xbar_random/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
- Test chip_sw_i2c_host_tx_rx_idx1 has 1 failures.
  - 2.chip_sw_i2c_host_tx_rx_idx1.43646101297549839781316083434045388411153629059912155982507812423934902306158
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx_idx1/latest/run.log
```
  Job timed out after 60 minutes
```
- ... and 28 more tests.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
- Test chip_sw_all_escalation_resets has 3 failures.
  - 8.chip_sw_all_escalation_resets.81083333219637651092622325607640862201918007375372860319539141459644318845526
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2432.887800 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2432.887800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 12.chip_sw_all_escalation_resets.44268446971482437377727839845584986129698165858070213835754279735971476169584
    Line 406, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3331.145944 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3331.145944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 2 failures:

Test chip_sw_power_sleep_load has 2 failures.

1.chip_sw_power_sleep_load.54723026574974539488899375184692220276086898621456533765792391087228540481178
Line 568, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_sleep_load/latest/run.log

  UVM_ERROR @ 2960.609000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2960.609000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_sw_power_sleep_load.37644766020133070889800816319501931569021356637283626069413044458164214648076
Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_sleep_load/latest/run.log

  UVM_ERROR @ 3758.660000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3758.660000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 2 failures:
- Test chip_sw_ast_clk_rst_inputs has 2 failures.
  - 1.chip_sw_ast_clk_rst_inputs.67263198586529897784344890177168418710692876436256657267450620652195659007605
    Line 493, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 16262.012363 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 16262.012363 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.chip_sw_ast_clk_rst_inputs.108442968548611606053372973183316615455071312364298019710599144325310410335165
    Line 410, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 19937.215024 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 19937.215024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 2.chip_sw_spi_device_pass_through_collision.49429550663785209870713049474371415720492036186109614744215414997275496771925
    Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3502.619290 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3502.619290 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@81571) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

2.chip_sw_rstmgr_cpu_info.58787854930183227505793915308900917728953651471070644707878919538700915301185
Line 431, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4493.482262 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@81571) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4493.482262 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.14903187965081130864047992301613659001087010142196569685993922928723183539408
    Line 410, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34747.052412 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34747.052412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 2.chip_sw_alert_test.68902048804439620064579648366087782469124732635235337338154385891416810970571
    Line 393, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2890.453673 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2890.453673 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 2.chip_sw_hmac_oneshot.92628752280215023032970725389814010907570501113703632514706153641626999475481
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 3079.004544 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 3079.004544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:594) virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 21.chip_sw_all_escalation_resets.95257318950303721084145424747871694505141585351541601533649503248281527154703
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/21.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3233.808470 us: (cip_base_vseq.sv:594) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
  UVM_INFO @ 3233.808470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```