ADC_CTRL Simulation Results

Sunday September 28 2025 00:12:59 UTC

GitHub Revision: `c5877ed`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	21.370s	6.051ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.890s	1.031ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.690s	510.234us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.783m	51.634ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	6.270s	1.160ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	3.250s	588.592us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.690s	510.234us	20	20	100.00
		adc_ctrl_csr_aliasing	6.270s	1.160ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	21.861m	485.435ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	21.216m	499.294ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	21.690m	497.626ms	49	50	98.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.689m	503.427ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	25.993m	552.032ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	28.137m	605.570ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	24.788m	600.000ms	47	50	94.00
V2	clock_gating	adc_ctrl_clock_gating	21.469m	558.739ms	35	50	70.00
V2	poweron_counter	adc_ctrl_poweron_counter	17.940s	5.316ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.991m	42.083ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	6.384m	132.849ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	55.298m	10.000s	47	50	94.00
V2	alert_test	adc_ctrl_alert_test	2.570s	521.757us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	2.560s	528.386us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	5.070s	465.817us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	5.070s	465.817us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.890s	1.031ms	5	5	100.00
		adc_ctrl_csr_rw	2.690s	510.234us	20	20	100.00
		adc_ctrl_csr_aliasing	6.270s	1.160ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	21.630s	5.387ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.890s	1.031ms	5	5	100.00
		adc_ctrl_csr_rw	2.690s	510.234us	20	20	100.00
		adc_ctrl_csr_aliasing	6.270s	1.160ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	21.630s	5.387ms	20	20	100.00
V2		TOTAL			718	740	97.03
V2S	tl_intg_err	adc_ctrl_sec_cm	17.500s	8.234ms	5	5	100.00
		adc_ctrl_tl_intg_err	19.660s	8.478ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	19.660s	8.478ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	31.460m	10.000s	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			893	920	97.07

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.26	99.05	96.03	100.00	100.00	98.64	95.95	91.18

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 17 failures:

Test adc_ctrl_clock_gating has 10 failures.

1.adc_ctrl_clock_gating.4043276587997360857936682980227539976980621631796453730790321326056474161749
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest/run.log

  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.adc_ctrl_clock_gating.109178311984578322727585308847216825689376831021316053228809687090100906420139
Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest/run.log

  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test adc_ctrl_stress_all has 2 failures.

5.adc_ctrl_stress_all.106712907107297555844126457857434827381604110925461757630034297113300828659060
Line 246, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.adc_ctrl_stress_all.78635218963733852218766435173516667338111848573967360654271444195579917357276
Line 189, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all_with_rand_reset has 2 failures.

20.adc_ctrl_stress_all_with_rand_reset.3985200633693682068709835654290068310261199573709203461678269354051584220900
Line 168, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.adc_ctrl_stress_all_with_rand_reset.95621836840923735088791637709369228934430531377181061912828578218133236197272
Line 235, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_filters_both has 3 failures.

32.adc_ctrl_filters_both.31889824612880022720066053121017860675013936234719606692800680562053920208532
Line 180, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/32.adc_ctrl_filters_both/latest/run.log

  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.adc_ctrl_filters_both.19762645417304273782936367598767117113879354652292029381770532728074491284385
Line 180, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/35.adc_ctrl_filters_both/latest/run.log

  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 8 failures:
- Test adc_ctrl_clock_gating has 5 failures.
  - 6.adc_ctrl_clock_gating.44451052154148787411996117251580605842294905632448270406844224506733190473924
    Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest/run.log
```
  UVM_ERROR @ 60745025694 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 60745025694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 12.adc_ctrl_clock_gating.46722001147213607852684388235669977494274796100360907333073337878777876684189
    Line 182, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/12.adc_ctrl_clock_gating/latest/run.log
```
  UVM_ERROR @ 361088644728 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 361088644728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
- Test adc_ctrl_stress_all_with_rand_reset has 3 failures.
  - 23.adc_ctrl_stress_all_with_rand_reset.10631084321384267022201745127564744468584045639484029776369728542204621635705
    Line 189, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13082283525 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 13082283525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 46.adc_ctrl_stress_all_with_rand_reset.20596966601468001310727875997592132641558670392556963409659718493999657641853
    Line 200, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3171212493 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 3171212493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 2 failures:
- Test adc_ctrl_stress_all has 1 failures.
  - 18.adc_ctrl_stress_all.99433248806298500638549168058319522004639744996742853862774981738940498826252
    Line 149, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 186560867897 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 186560867897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test adc_ctrl_filters_interrupt has 1 failures.
  - 37.adc_ctrl_filters_interrupt.49973884792502496042715919060681370396709479289234080371259691047116392341935
    Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt/latest/run.log
```
  UVM_ERROR @ 163937703512 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 163937703512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```