AES/MASKED Simulation Results

Sunday September 28 2025 00:12:59 UTC

GitHub Revision: `c5877ed`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	55.110us	1	1	100.00
V1	smoke	aes_smoke	9.000s	804.957us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	180.045us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	56.650us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	896.216us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	184.937us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	77.089us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	56.650us	20	20	100.00
		aes_csr_aliasing	4.000s	184.937us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	804.957us	50	50	100.00
		aes_config_error	11.000s	687.402us	50	50	100.00
		aes_stress	50.000s	2.495ms	50	50	100.00
V2	key_length	aes_smoke	9.000s	804.957us	50	50	100.00
		aes_config_error	11.000s	687.402us	50	50	100.00
		aes_stress	50.000s	2.495ms	50	50	100.00
V2	back2back	aes_stress	50.000s	2.495ms	50	50	100.00
		aes_b2b	47.000s	920.761us	50	50	100.00
V2	backpressure	aes_stress	50.000s	2.495ms	50	50	100.00
V2	multi_message	aes_smoke	9.000s	804.957us	50	50	100.00
		aes_config_error	11.000s	687.402us	50	50	100.00
		aes_stress	50.000s	2.495ms	50	50	100.00
		aes_alert_reset	9.000s	368.004us	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	156.288us	50	50	100.00
		aes_config_error	11.000s	687.402us	50	50	100.00
		aes_alert_reset	9.000s	368.004us	50	50	100.00
V2	trigger_clear_test	aes_clear	30.000s	4.287ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	2.334ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	368.004us	50	50	100.00
V2	stress	aes_stress	50.000s	2.495ms	50	50	100.00
V2	sideload	aes_stress	50.000s	2.495ms	50	50	100.00
		aes_sideload	7.000s	1.761ms	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	293.231us	50	50	100.00
V2	stress_all	aes_stress_all	1.050m	2.555ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	68.432us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	345.519us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	345.519us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	180.045us	5	5	100.00
		aes_csr_rw	3.000s	56.650us	20	20	100.00
		aes_csr_aliasing	4.000s	184.937us	5	5	100.00
		aes_same_csr_outstanding	3.000s	218.084us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	180.045us	5	5	100.00
		aes_csr_rw	3.000s	56.650us	20	20	100.00
		aes_csr_aliasing	4.000s	184.937us	5	5	100.00
		aes_same_csr_outstanding	3.000s	218.084us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	55.000s	3.070ms	50	50	100.00
V2S	fault_inject	aes_fi	7.000s	644.942us	50	50	100.00
		aes_control_fi	1.000m	10.006ms	275	300	91.67
		aes_cipher_fi	1.000m	10.002ms	345	350	98.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	68.473us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	68.473us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	68.473us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	68.473us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	193.123us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	19.000s	2.274ms	5	5	100.00
		aes_tl_intg_err	5.000s	652.760us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	652.760us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	368.004us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	68.473us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	804.957us	50	50	100.00
		aes_stress	50.000s	2.495ms	50	50	100.00
		aes_alert_reset	9.000s	368.004us	50	50	100.00
		aes_core_fi	1.133m	10.061ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	68.473us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	103.907us	50	50	100.00
		aes_stress	50.000s	2.495ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	50.000s	2.495ms	50	50	100.00
		aes_sideload	7.000s	1.761ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	103.907us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	103.907us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	103.907us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	103.907us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	103.907us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	50.000s	2.495ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	50.000s	2.495ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	644.942us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	644.942us	50	50	100.00
		aes_control_fi	1.000m	10.006ms	275	300	91.67
		aes_cipher_fi	1.000m	10.002ms	345	350	98.57
		aes_ctr_fi	5.000s	152.715us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	644.942us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	644.942us	50	50	100.00
		aes_control_fi	1.000m	10.006ms	275	300	91.67
		aes_cipher_fi	1.000m	10.002ms	345	350	98.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.000m	10.002ms	345	350	98.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	644.942us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	644.942us	50	50	100.00
		aes_control_fi	1.000m	10.006ms	275	300	91.67
		aes_ctr_fi	5.000s	152.715us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	644.942us	50	50	100.00
		aes_control_fi	1.000m	10.006ms	275	300	91.67
		aes_cipher_fi	1.000m	10.002ms	345	350	98.57
		aes_ctr_fi	5.000s	152.715us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	368.004us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	644.942us	50	50	100.00
		aes_control_fi	1.000m	10.006ms	275	300	91.67
		aes_cipher_fi	1.000m	10.002ms	345	350	98.57
		aes_ctr_fi	5.000s	152.715us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	644.942us	50	50	100.00
		aes_control_fi	1.000m	10.006ms	275	300	91.67
		aes_cipher_fi	1.000m	10.002ms	345	350	98.57
		aes_ctr_fi	5.000s	152.715us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	644.942us	50	50	100.00
		aes_control_fi	1.000m	10.006ms	275	300	91.67
		aes_ctr_fi	5.000s	152.715us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	644.942us	50	50	100.00
		aes_control_fi	1.000m	10.006ms	275	300	91.67
		aes_cipher_fi	1.000m	10.002ms	345	350	98.57
V2S		TOTAL			953	985	96.75
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	30.000s	7.924ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1560	1602	97.38

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.38	98.64	96.54	99.45	95.43	97.99	100.00	98.36	98.59

Failure Buckets

Job timed out after * minutes has 15 failures:
- Test aes_control_fi has 15 failures.
  - 21.aes_control_fi.95291222341528655182419395399453850200621281847058972002206383442649216362739
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/21.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 39.aes_control_fi.69423812372028540082385288097726742110990590448958620689009239952994218258044
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/39.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 13 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 8.aes_control_fi.103673662289103614723926511653544702749530113308095142772086176902046088355183
    Line 138, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006258272 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006258272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 10.aes_control_fi.106551270584142327439631796992677307724311723033362830338714915662703389445299
    Line 148, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010126778 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010126778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 21.aes_cipher_fi.3093647074743249248155838516011803191072302743170344978445718141220071335885
    Line 136, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/21.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10033502319 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10033502319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 125.aes_cipher_fi.47474947640259507028364900571710454524032343369960789351062314390942036358803
    Line 131, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/125.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013716306 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013716306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.87931396644931946050923296954963029783589504635079084074576661689553369069530
Line 573, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1050822724 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1050822724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.94061591627391089938610226431734703988293385571157124257032284550033094991438
Line 933, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 963577216 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 963577216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 2.aes_stress_all_with_rand_reset.51667420577277030792072710552150973418178004701219604953096626381594923889496
    Line 1125, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1350512936 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1350512936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.aes_stress_all_with_rand_reset.101727221829009693629095020707956618266685431123212362095519329328540447421763
    Line 312, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 396393590 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 396393590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 1.aes_stress_all_with_rand_reset.114325110561470848774518394110239556851164114635656350334878471798181224666572
    Line 551, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 839927240 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 839927240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.aes_stress_all_with_rand_reset.55471623358549221149802054298710148598730054948181418946427625628756105916529
    Line 534, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 771815073 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 771815073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 5.aes_core_fi.21876948272419592772925473355736507326902802940697949932917963584594889125186
    Line 149, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/5.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10060501307 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10060501307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 50.aes_core_fi.95236613939814056790936448338631636941831504526899278364687321560478093814506
    Line 138, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/50.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012623175 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012623175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.90110006995168705334865366707433139606432331622408927307158087582715408511513
    Line 547, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2770309426 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 2770309426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```