AES/UNMASKED Simulation Results

Sunday September 28 2025 00:12:59 UTC

GitHub Revision: `c5877ed`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	34.000s	85.226us	1	1	100.00
V1	smoke	aes_smoke	34.000s	60.014us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	69.313us	5	5	100.00
V1	csr_rw	aes_csr_rw	2.000s	57.592us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.900ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	364.345us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	72.781us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	2.000s	57.592us	20	20	100.00
		aes_csr_aliasing	4.000s	364.345us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	34.000s	60.014us	50	50	100.00
		aes_config_error	34.000s	127.690us	50	50	100.00
		aes_stress	34.000s	237.964us	50	50	100.00
V2	key_length	aes_smoke	34.000s	60.014us	50	50	100.00
		aes_config_error	34.000s	127.690us	50	50	100.00
		aes_stress	34.000s	237.964us	50	50	100.00
V2	back2back	aes_stress	34.000s	237.964us	50	50	100.00
		aes_b2b	36.000s	438.415us	50	50	100.00
V2	backpressure	aes_stress	34.000s	237.964us	50	50	100.00
V2	multi_message	aes_smoke	34.000s	60.014us	50	50	100.00
		aes_config_error	34.000s	127.690us	50	50	100.00
		aes_stress	34.000s	237.964us	50	50	100.00
		aes_alert_reset	34.000s	108.002us	50	50	100.00
V2	failure_test	aes_man_cfg_err	34.000s	63.759us	50	50	100.00
		aes_config_error	34.000s	127.690us	50	50	100.00
		aes_alert_reset	34.000s	108.002us	50	50	100.00
V2	trigger_clear_test	aes_clear	35.000s	961.200us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	36.000s	178.977us	1	1	100.00
V2	reset_recovery	aes_alert_reset	34.000s	108.002us	50	50	100.00
V2	stress	aes_stress	34.000s	237.964us	50	50	100.00
V2	sideload	aes_stress	34.000s	237.964us	50	50	100.00
		aes_sideload	34.000s	155.882us	50	50	100.00
V2	deinitialization	aes_deinit	34.000s	71.433us	50	50	100.00
V2	stress_all	aes_stress_all	37.000s	939.260us	10	10	100.00
V2	alert_test	aes_alert_test	32.000s	82.382us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	1.126ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	1.126ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	69.313us	5	5	100.00
		aes_csr_rw	2.000s	57.592us	20	20	100.00
		aes_csr_aliasing	4.000s	364.345us	5	5	100.00
		aes_same_csr_outstanding	3.000s	79.070us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	69.313us	5	5	100.00
		aes_csr_rw	2.000s	57.592us	20	20	100.00
		aes_csr_aliasing	4.000s	364.345us	5	5	100.00
		aes_same_csr_outstanding	3.000s	79.070us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	34.000s	366.932us	50	50	100.00
V2S	fault_inject	aes_fi	33.000s	271.216us	49	50	98.00
		aes_control_fi	46.000s	10.005ms	281	300	93.67
		aes_cipher_fi	48.000s	10.009ms	329	350	94.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	81.884us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	81.884us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	81.884us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	81.884us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	180.850us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	33.000s	444.353us	5	5	100.00
		aes_tl_intg_err	4.000s	1.119ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	4.000s	1.119ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	34.000s	108.002us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	81.884us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	34.000s	60.014us	50	50	100.00
		aes_stress	34.000s	237.964us	50	50	100.00
		aes_alert_reset	34.000s	108.002us	50	50	100.00
		aes_core_fi	1.567m	10.028ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	81.884us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	34.000s	59.013us	50	50	100.00
		aes_stress	34.000s	237.964us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	34.000s	237.964us	50	50	100.00
		aes_sideload	34.000s	155.882us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	34.000s	59.013us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	34.000s	59.013us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	34.000s	59.013us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	34.000s	59.013us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	34.000s	59.013us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	34.000s	237.964us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	34.000s	237.964us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	33.000s	271.216us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	33.000s	271.216us	49	50	98.00
		aes_control_fi	46.000s	10.005ms	281	300	93.67
		aes_cipher_fi	48.000s	10.009ms	329	350	94.00
		aes_ctr_fi	33.000s	69.245us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	33.000s	271.216us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	33.000s	271.216us	49	50	98.00
		aes_control_fi	46.000s	10.005ms	281	300	93.67
		aes_cipher_fi	48.000s	10.009ms	329	350	94.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.009ms	329	350	94.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	33.000s	271.216us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	33.000s	271.216us	49	50	98.00
		aes_control_fi	46.000s	10.005ms	281	300	93.67
		aes_ctr_fi	33.000s	69.245us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	33.000s	271.216us	49	50	98.00
		aes_control_fi	46.000s	10.005ms	281	300	93.67
		aes_cipher_fi	48.000s	10.009ms	329	350	94.00
		aes_ctr_fi	33.000s	69.245us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	34.000s	108.002us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	33.000s	271.216us	49	50	98.00
		aes_control_fi	46.000s	10.005ms	281	300	93.67
		aes_cipher_fi	48.000s	10.009ms	329	350	94.00
		aes_ctr_fi	33.000s	69.245us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	33.000s	271.216us	49	50	98.00
		aes_control_fi	46.000s	10.005ms	281	300	93.67
		aes_cipher_fi	48.000s	10.009ms	329	350	94.00
		aes_ctr_fi	33.000s	69.245us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	33.000s	271.216us	49	50	98.00
		aes_control_fi	46.000s	10.005ms	281	300	93.67
		aes_ctr_fi	33.000s	69.245us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	33.000s	271.216us	49	50	98.00
		aes_control_fi	46.000s	10.005ms	281	300	93.67
		aes_cipher_fi	48.000s	10.009ms	329	350	94.00
V2S		TOTAL			941	985	95.53
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	45.000s	5.939ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1548	1602	96.63

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.21	97.66	94.80	98.71	93.17	98.07	92.59	98.08	98.19

Failure Buckets

Job timed out after * minutes has 24 failures:
- Test aes_cipher_fi has 13 failures.
  - 10.aes_cipher_fi.35594838937026477642510256295609594693628858510518840498563327711833376997406
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/10.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 35.aes_cipher_fi.32427243476827167467706909261055342711959548294736314496143217861417670661664
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/35.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 11 more failures.
- Test aes_control_fi has 11 failures.
  - 15.aes_control_fi.5819797636084566127202200936934975894503082201791788203294768043127331368309
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 30.aes_control_fi.26320066661357942149468208115637461836290735463125418780782220287073658553407
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/30.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 9 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 0.aes_control_fi.61662332613840119616859306330963779156167468455968329309962141503605307288018
    Line 139, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005014019 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005014019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 17.aes_control_fi.64053058781272889641619696983082854258407125573856949878206589999452597267987
    Line 139, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/17.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003530905 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003530905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 7.aes_cipher_fi.69295401633240694315054884466803755582301814263142150267528175835891688960365
    Line 146, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/7.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014179483 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014179483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 47.aes_cipher_fi.55788167134735923075780927055937359921553394524303127863419774207331702808680
    Line 136, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/47.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10032770247 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10032770247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

1.aes_stress_all_with_rand_reset.52351817057935876297303710887191635147340724152005019132650511919099181011562
Line 559, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 379462416 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 379462416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.13995275753719213071613755660911216534647860891498350140339218906313762488278
Line 1047, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4031212660 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4031212660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 0.aes_stress_all_with_rand_reset.37833724235084603151921564515032016362942132255314644837496545117411544172712
    Line 908, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 5938609187 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 5938609187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.aes_stress_all_with_rand_reset.78061171184632534400125323778448103281039174632937533050195167057478971846005
    Line 146, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  21044430 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  21044430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 10.aes_core_fi.64293666403756226957145588971970307615894720228442205554475037700214408364081
    Line 146, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/10.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005818974 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005818974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 15.aes_core_fi.101989485092063339453392768193071463212170059736731523252233891799517157977446
    Line 146, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/15.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010553483 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010553483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.4648289864069799372745123098718081597034766075706099114478772154743722479616
    Line 1327, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1956900667 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1956900667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 5.aes_core_fi.107949951889486640877030758525603999139311045103840708371006932919582277121588
    Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/5.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10028141208 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x362f7c84, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
  UVM_INFO @ 10028141208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 27.aes_fi.44103562513446866105040861912701872771198530587691262903753045791967344398632
    Line 5750, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/27.aes_fi/latest/run.log
```
  UVM_FATAL @ 448565792 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 448565792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```