CSRNG Simulation Results

Sunday September 28 2025 00:12:59 UTC

GitHub Revision: `c5877ed`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	147.859us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	123.839us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	59.101us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	33.000s	2.151ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	117.731us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	4.000s	39.817us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	59.101us	20	20	100.00
		csrng_csr_aliasing	5.000s	117.731us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	21.000s	1.367ms	182	200	91.00
V2	alerts	csrng_alert	57.000s	4.788ms	500	500	100.00
V2	err	csrng_err	8.000s	26.140us	471	500	94.20
V2	cmds	csrng_cmds	11.983m	61.868ms	50	50	100.00
V2	life cycle	csrng_cmds	11.983m	61.868ms	50	50	100.00
V2	stress_all	csrng_stress_all	20.417m	93.443ms	49	50	98.00
V2	intr_test	csrng_intr_test	3.000s	23.161us	50	50	100.00
V2	alert_test	csrng_alert_test	6.000s	269.780us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	11.000s	254.153us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	11.000s	254.153us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	123.839us	5	5	100.00
		csrng_csr_rw	4.000s	59.101us	20	20	100.00
		csrng_csr_aliasing	5.000s	117.731us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	83.386us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	123.839us	5	5	100.00
		csrng_csr_rw	4.000s	59.101us	20	20	100.00
		csrng_csr_aliasing	5.000s	117.731us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	83.386us	20	20	100.00
V2		TOTAL			1392	1440	96.67
V2S	tl_intg_err	csrng_sec_cm	8.000s	196.941us	5	5	100.00
		csrng_tl_intg_err	11.000s	703.639us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	6.000s	16.778us	50	50	100.00
		csrng_csr_rw	4.000s	59.101us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	57.000s	4.788ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	20.417m	93.443ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	21.000s	1.367ms	182	200	91.00
		csrng_err	8.000s	26.140us	471	500	94.20
		csrng_sec_cm	8.000s	196.941us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	21.000s	1.367ms	182	200	91.00
		csrng_err	8.000s	26.140us	471	500	94.20
		csrng_sec_cm	8.000s	196.941us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	21.000s	1.367ms	182	200	91.00
		csrng_err	8.000s	26.140us	471	500	94.20
		csrng_sec_cm	8.000s	196.941us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	21.000s	1.367ms	182	200	91.00
		csrng_err	8.000s	26.140us	471	500	94.20
		csrng_sec_cm	8.000s	196.941us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	21.000s	1.367ms	182	200	91.00
		csrng_err	8.000s	26.140us	471	500	94.20
		csrng_sec_cm	8.000s	196.941us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	21.000s	1.367ms	182	200	91.00
		csrng_err	8.000s	26.140us	471	500	94.20
		csrng_sec_cm	8.000s	196.941us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	21.000s	1.367ms	182	200	91.00
		csrng_err	8.000s	26.140us	471	500	94.20
		csrng_sec_cm	8.000s	196.941us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	57.000s	4.788ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	21.000s	1.367ms	182	200	91.00
		csrng_err	8.000s	26.140us	471	500	94.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	20.417m	93.443ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	57.000s	4.788ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	11.000s	703.639us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	21.000s	1.367ms	182	200	91.00
		csrng_err	8.000s	26.140us	471	500	94.20
		csrng_sec_cm	8.000s	196.941us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	21.000s	1.367ms	182	200	91.00
		csrng_err	8.000s	26.140us	471	500	94.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	21.000s	1.367ms	182	200	91.00
		csrng_err	8.000s	26.140us	471	500	94.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	21.000s	1.367ms	182	200	91.00
		csrng_err	8.000s	26.140us	471	500	94.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	21.000s	1.367ms	182	200	91.00
		csrng_err	8.000s	26.140us	471	500	94.20
		csrng_sec_cm	8.000s	196.941us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	21.000s	1.367ms	182	200	91.00
		csrng_err	8.000s	26.140us	471	500	94.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	6.317m	19.698ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1582	1630	97.06

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.69	98.63	96.68	99.97	97.42	92.08	100.00	95.43	90.36

Failure Buckets

UVM_FATAL (csrng_base_vseq.sv:189) virtual_sequencer [csrng_err_vseq] has 15 failures:

Test csrng_err has 15 failures.

45.csrng_err.38937936934480394668384721171588928776056758056062691697897163193799272958996
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/45.csrng_err/latest/run.log

  UVM_FATAL @   3467194 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
       ----| PATH NOT FOUND
  UVM_INFO @   3467194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

63.csrng_err.28671239625811367834724775519208665381756085144109150815508295588931504652730
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/63.csrng_err/latest/run.log

  UVM_FATAL @   1916281 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
       ----| PATH NOT FOUND
  UVM_INFO @   1916281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

UVM_FATAL (csrng_base_vseq.sv:184) virtual_sequencer [csrng_err_vseq] has 14 failures:

Test csrng_err has 14 failures.

18.csrng_err.43799575522989162238787083652327208886784628541440255146624728798042382225500
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/18.csrng_err/latest/run.log

  UVM_FATAL @   1868744 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
       ----| PATH NOT FOUND
  UVM_INFO @   1868744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.csrng_err.19300051818104168208052472992575799261950323553567577947541411281903927073676
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/26.csrng_err/latest/run.log

  UVM_FATAL @  37051845 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
       ----| PATH NOT FOUND
  UVM_INFO @  37051845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

UVM_FATAL (csrng_base_vseq.sv:189) virtual_sequencer [csrng_intr_vseq] has 9 failures:

Test csrng_intr has 9 failures.

4.csrng_intr.99316339246685378385756008917960595329975403563847332295819541729175511315811
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/4.csrng_intr/latest/run.log

  UVM_FATAL @ 152515464 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
       ----| PATH NOT FOUND
  UVM_INFO @ 152515464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.csrng_intr.61179587535027582808326712272254100664513507698133893830112769140586397095996
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/8.csrng_intr/latest/run.log

  UVM_FATAL @ 245466571 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
       ----| PATH NOT FOUND
  UVM_INFO @ 245466571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (csrng_base_vseq.sv:184) virtual_sequencer [csrng_intr_vseq] has 8 failures:

Test csrng_intr has 8 failures.

6.csrng_intr.95642831461623824230130361285486136026008383131617114156928380075122409766410
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/6.csrng_intr/latest/run.log

  UVM_FATAL @  77058992 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
       ----| PATH NOT FOUND
  UVM_INFO @  77058992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

61.csrng_intr.36741268591298338598020745161463709851788501455913370765418950387235347818014
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/61.csrng_intr/latest/run.log

  UVM_FATAL @ 173275078 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
       ----| PATH NOT FOUND
  UVM_INFO @ 173275078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 27.csrng_stress_all.49636494130204303484020442181634915437169377947903513476692644474293300725793
    Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/27.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 5623609780 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 5623609780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,515): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 1 failures:

Test csrng_intr has 1 failures.

62.csrng_intr.32707836966490429865055591536564728128878082289975050479206319177086304328904
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/62.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,515): (time 106916366 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 106916366 ps: (csrng_cmd_stage.sv:515) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 106916366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---