EDN Simulation Results

Sunday September 28 2025 00:12:59 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.420s 20.392us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.230s 27.293us 5 5 100.00
V1 csr_rw edn_csr_rw 1.300s 28.068us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.180s 173.462us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.330s 20.893us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.210s 33.856us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.300s 28.068us 20 20 100.00
edn_csr_aliasing 1.330s 20.893us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.641m 10.465ms 300 300 100.00
V2 csrng_commands edn_genbits 1.641m 10.465ms 300 300 100.00
V2 genbits edn_genbits 1.641m 10.465ms 300 300 100.00
V2 interrupts edn_intr 1.690s 21.421us 50 50 100.00
V2 alerts edn_alert 1.800s 369.636us 200 200 100.00
V2 errs edn_err 1.660s 23.433us 100 100 100.00
V2 disable edn_disable 1.330s 14.692us 50 50 100.00
edn_disable_auto_req_mode 1.830s 48.460us 50 50 100.00
V2 stress_all edn_stress_all 7.770s 389.754us 50 50 100.00
V2 intr_test edn_intr_test 1.200s 41.479us 50 50 100.00
V2 alert_test edn_alert_test 1.610s 28.432us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.800s 128.859us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 3.800s 128.859us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.230s 27.293us 5 5 100.00
edn_csr_rw 1.300s 28.068us 20 20 100.00
edn_csr_aliasing 1.330s 20.893us 5 5 100.00
edn_same_csr_outstanding 1.740s 226.417us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.230s 27.293us 5 5 100.00
edn_csr_rw 1.300s 28.068us 20 20 100.00
edn_csr_aliasing 1.330s 20.893us 5 5 100.00
edn_same_csr_outstanding 1.740s 226.417us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 6.400s 2.765ms 5 5 100.00
edn_tl_intg_err 2.880s 160.985us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.320s 38.434us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.800s 369.636us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.400s 2.765ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.400s 2.765ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.400s 2.765ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.400s 2.765ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.800s 369.636us 200 200 100.00
edn_sec_cm 6.400s 2.765ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.800s 369.636us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.880s 160.985us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.925m 24.613ms 28 50 56.00
V3 TOTAL 28 50 56.00
TOTAL 1108 1130 98.05

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.71 98.87 94.05 97.02 93.02 96.33 97.56 93.13

Failure Buckets