ENTROPY_SRC/RNG_4BITS Simulation Results

Sunday September 28 2025 00:12:59 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 3.000s 49.179us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 21.000s 50.873us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 18.000s 23.802us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 20.000s 88.541us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 14.000s 423.540us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 3.000s 43.205us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 18.000s 23.802us 20 20 100.00
entropy_src_csr_aliasing 14.000s 423.540us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 3.000s 49.179us 50 50 100.00
entropy_src_rng 8.700m 20.092ms 298 300 99.33
entropy_src_fw_ov 9.533m 20.045ms 295 300 98.33
V2 firmware_mode entropy_src_fw_ov 9.533m 20.045ms 295 300 98.33
V2 rng_mode entropy_src_rng 8.700m 20.092ms 298 300 99.33
V2 rng_max_rate entropy_src_rng_max_rate 13.667m 20.015ms 399 400 99.75
V2 health_checks entropy_src_rng 8.700m 20.092ms 298 300 99.33
V2 conditioning entropy_src_rng 8.700m 20.092ms 298 300 99.33
V2 interrupts entropy_src_rng 8.700m 20.092ms 298 300 99.33
entropy_src_intr 38.000s 503.849us 50 50 100.00
V2 alerts entropy_src_rng 8.700m 20.092ms 298 300 99.33
entropy_src_functional_alerts 8.000s 178.729us 50 50 100.00
V2 stress_all entropy_src_stress_all 6.650m 16.054ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 6.633m 10.013ms 989 1000 98.90
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 24.000s 294.017us 50 50 100.00
V2 intr_test entropy_src_intr_test 30.000s 15.224us 50 50 100.00
V2 alert_test entropy_src_alert_test 3.000s 43.224us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 36.000s 368.143us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 36.000s 368.143us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 21.000s 50.873us 5 5 100.00
entropy_src_csr_rw 18.000s 23.802us 20 20 100.00
entropy_src_csr_aliasing 14.000s 423.540us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 23.754us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 21.000s 50.873us 5 5 100.00
entropy_src_csr_rw 18.000s 23.802us 20 20 100.00
entropy_src_csr_aliasing 14.000s 423.540us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 23.754us 20 20 100.00
V2 TOTAL 2321 2340 99.19
V2S tl_intg_err entropy_src_sec_cm 3.000s 694.195us 5 5 100.00
entropy_src_tl_intg_err 36.000s 616.260us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 8.700m 20.092ms 298 300 99.33
entropy_src_cfg_regwen 3.000s 103.511us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 8.700m 20.092ms 298 300 99.33
V2S sec_cm_config_redun entropy_src_rng 8.700m 20.092ms 298 300 99.33
V2S sec_cm_intersig_mubi entropy_src_rng 8.700m 20.092ms 298 300 99.33
entropy_src_fw_ov 9.533m 20.045ms 295 300 98.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 6.633m 10.013ms 989 1000 98.90
entropy_src_sec_cm 3.000s 694.195us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 6.633m 10.013ms 989 1000 98.90
entropy_src_sec_cm 3.000s 694.195us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 8.700m 20.092ms 298 300 99.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 6.633m 10.013ms 989 1000 98.90
entropy_src_sec_cm 3.000s 694.195us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 6.633m 10.013ms 989 1000 98.90
entropy_src_sec_cm 3.000s 694.195us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 6.633m 10.013ms 989 1000 98.90
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 8.000s 178.729us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 36.000s 616.260us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 8.017m 20.039ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 2551 2570 99.26

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
94.17 97.40 93.35 98.36 95.21 79.78 97.92 89.27 96.47

Failure Buckets