HMAC Simulation Results

Sunday September 28 2025 00:12:59 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	15.540s	9.719ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.230s	59.766us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.340s	28.011us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.760s	1.381ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.510s	203.818us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	14.986m	210.588ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.340s	28.011us	20	20	100.00
		hmac_csr_aliasing	8.510s	203.818us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.661m	29.986ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.869m	3.115ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.900m	40.044ms	30	30	100.00
		hmac_test_sha384_vectors	9.931m	130.262ms	75	75	100.00
		hmac_test_sha512_vectors	8.765m	28.358ms	75	75	100.00
		hmac_test_hmac256_vectors	15.560s	1.455ms	50	50	100.00
		hmac_test_hmac384_vectors	17.660s	391.985us	60	60	100.00
		hmac_test_hmac512_vectors	21.710s	430.383us	75	75	100.00
V2	burst_wr	hmac_burst_wr	38.450s	5.025ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	29.122m	9.608ms	10	10	100.00
V2	error	hmac_error	1.295m	5.827ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.778m	6.021ms	10	10	100.00
V2	save_and_restore	hmac_smoke	15.540s	9.719ms	10	10	100.00
		hmac_long_msg	1.661m	29.986ms	10	10	100.00
		hmac_back_pressure	1.869m	3.115ms	25	25	100.00
		hmac_datapath_stress	29.122m	9.608ms	10	10	100.00
		hmac_burst_wr	38.450s	5.025ms	50	50	100.00
		hmac_stress_all	37.161m	325.121ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	15.540s	9.719ms	10	10	100.00
		hmac_long_msg	1.661m	29.986ms	10	10	100.00
		hmac_back_pressure	1.869m	3.115ms	25	25	100.00
		hmac_datapath_stress	29.122m	9.608ms	10	10	100.00
		hmac_wipe_secret	1.778m	6.021ms	10	10	100.00
		hmac_test_sha256_vectors	4.900m	40.044ms	30	30	100.00
		hmac_test_sha384_vectors	9.931m	130.262ms	75	75	100.00
		hmac_test_sha512_vectors	8.765m	28.358ms	75	75	100.00
		hmac_test_hmac256_vectors	15.560s	1.455ms	50	50	100.00
		hmac_test_hmac384_vectors	17.660s	391.985us	60	60	100.00
		hmac_test_hmac512_vectors	21.710s	430.383us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	15.540s	9.719ms	10	10	100.00
		hmac_long_msg	1.661m	29.986ms	10	10	100.00
		hmac_back_pressure	1.869m	3.115ms	25	25	100.00
		hmac_datapath_stress	29.122m	9.608ms	10	10	100.00
		hmac_burst_wr	38.450s	5.025ms	50	50	100.00
		hmac_error	1.295m	5.827ms	10	10	100.00
		hmac_wipe_secret	1.778m	6.021ms	10	10	100.00
		hmac_test_sha256_vectors	4.900m	40.044ms	30	30	100.00
		hmac_test_sha384_vectors	9.931m	130.262ms	75	75	100.00
		hmac_test_sha512_vectors	8.765m	28.358ms	75	75	100.00
		hmac_test_hmac256_vectors	15.560s	1.455ms	50	50	100.00
		hmac_test_hmac384_vectors	17.660s	391.985us	60	60	100.00
		hmac_test_hmac512_vectors	21.710s	430.383us	75	75	100.00
		hmac_stress_all	37.161m	325.121ms	50	50	100.00
V2	stress_all	hmac_stress_all	37.161m	325.121ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.950s	21.404us	50	50	100.00
V2	intr_test	hmac_intr_test	1.010s	69.959us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.830s	236.803us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.830s	236.803us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.230s	59.766us	5	5	100.00
		hmac_csr_rw	1.340s	28.011us	20	20	100.00
		hmac_csr_aliasing	8.510s	203.818us	5	5	100.00
		hmac_same_csr_outstanding	3.100s	605.886us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.230s	59.766us	5	5	100.00
		hmac_csr_rw	1.340s	28.011us	20	20	100.00
		hmac_csr_aliasing	8.510s	203.818us	5	5	100.00
		hmac_same_csr_outstanding	3.100s	605.886us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	1.510s	449.858us	5	5	100.00
		hmac_tl_intg_err	4.770s	1.279ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.770s	1.279ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	15.540s	9.719ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	7.630s	140.141us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	9.180m	10.455ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	1.210s	18.134us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.18	99.95	96.85	100.00	100.00	99.83	97.61	100.00