I2C Simulation Results

Sunday September 28 2025 00:12:59 UTC

GitHub Revision: `c5877ed`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.774m	10.144ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	39.150s	1.474ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.020s	18.651us	5	5	100.00
V1	csr_rw	i2c_csr_rw	1.880s	3.219ms	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.740s	528.742us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.900s	447.225us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.660s	38.895us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.880s	3.219ms	20	20	100.00
		i2c_csr_aliasing	1.900s	447.225us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	8.500s	712.518us	2	50	4.00
V2	host_stress_all	i2c_host_stress_all	55.269m	51.539ms	9	50	18.00
V2	host_maxperf	i2c_host_perf	27.685m	49.686ms	50	50	100.00
V2	host_override	i2c_host_override	1.050s	26.239us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.628m	7.348ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.673m	9.631ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.780s	333.030us	50	50	100.00
		i2c_host_fifo_fmt_empty	21.620s	451.578us	50	50	100.00
		i2c_host_fifo_reset_rx	11.230s	805.678us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.132m	11.370ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	34.300s	3.209ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	5.150s	154.543us	17	50	34.00
V2	target_glitch	i2c_target_glitch	3.710s	465.154us	0	2	0.00
V2	target_stress_all	i2c_target_stress_all	24.083m	73.295ms	45	50	90.00
V2	target_maxperf	i2c_target_perf	8.350s	1.468ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	59.100s	1.344ms	50	50	100.00
		i2c_target_intr_smoke	10.970s	12.978ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.590s	323.324us	50	50	100.00
		i2c_target_fifo_reset_tx	2.370s	1.592ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	26.478m	70.049ms	50	50	100.00
		i2c_target_stress_rd	59.100s	1.344ms	50	50	100.00
		i2c_target_intr_stress_wr	6.616m	24.244ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	9.520s	5.906ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	2.639m	4.928ms	44	50	88.00
V2	bad_address	i2c_target_bad_addr	8.810s	1.627ms	49	50	98.00
V2	target_mode_glitch	i2c_target_hrst	36.760s	10.088ms	28	50	56.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	4.540s	645.501us	50	50	100.00
		i2c_target_fifo_watermarks_tx	2.170s	354.108us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	27.685m	49.686ms	50	50	100.00
		i2c_host_perf_precise	12.225m	23.220ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	34.300s	3.209ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	33.150s	2.250ms	48	50	96.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	4.190s	544.312us	50	50	100.00
		i2c_target_nack_acqfull_addr	4.400s	1.162ms	50	50	100.00
		i2c_target_nack_txstretch	2.260s	667.186us	36	50	72.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	30.430s	1.523ms	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.500s	1.059ms	50	50	100.00
V2	alert_test	i2c_alert_test	1.020s	26.144us	50	50	100.00
V2	intr_test	i2c_intr_test	1.060s	26.751us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.920s	462.890us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.920s	462.890us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.020s	18.651us	5	5	100.00
		i2c_csr_rw	1.880s	3.219ms	20	20	100.00
		i2c_csr_aliasing	1.900s	447.225us	5	5	100.00
		i2c_same_csr_outstanding	1.640s	102.596us	19	20	95.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.020s	18.651us	5	5	100.00
		i2c_csr_rw	1.880s	3.219ms	20	20	100.00
		i2c_csr_aliasing	1.900s	447.225us	5	5	100.00
		i2c_same_csr_outstanding	1.640s	102.596us	19	20	95.00
V2		TOTAL			1617	1792	90.23
V2S	tl_intg_err	i2c_tl_intg_err	2.660s	808.548us	20	20	100.00
		i2c_sec_cm	1.370s	128.038us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.660s	808.548us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	40.040s	3.869ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.470s	1.099ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	51.160s	1.598ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1797	2042	88.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.92	97.19	89.03	74.17	47.62	93.68	96.41	89.32

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 92 failures:

Test i2c_host_error_intr has 48 failures.

0.i2c_host_error_intr.29466907236773453017482589564213721986695426631947110474786196788864399168835
Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  76822878 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  76822878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_error_intr.31191488391914755268138260297326568084526100271200697960323869110964881295489
Line 123, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 167750298 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 167750298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 46 more failures.

Test i2c_target_stress_all_with_rand_reset has 4 failures.

0.i2c_target_stress_all_with_rand_reset.97056450845598080077462809421612408680828284991258149202564625779687696109619
Line 98, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 117252504 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 117252504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_target_stress_all_with_rand_reset.26552070650406050813781972944807882104622437931790693187634718706446936891757
Line 100, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1136694412 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 1136694412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test i2c_host_stress_all has 30 failures.

2.i2c_host_stress_all.110579494652117244813093786672781381101343528204736538204420608360792461150520
Line 129, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 54944273327 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 54944273327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_host_stress_all.31840340225476344041274440315410708292872742182245889552556899681698046670303
Line 111, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 146996899 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 146996899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 28 more failures.

Test i2c_host_mode_toggle has 10 failures.

6.i2c_host_mode_toggle.63983340483324460639096813689592400877717346942775216091750902490704021369465
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  18098028 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  18098028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.i2c_host_mode_toggle.63641420817716379014531379431661337739395371451996207172264570701386029460747
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/11.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  14224570 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  14224570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 29 failures:
- Test i2c_target_unexp_stop has 29 failures.
  - 1.i2c_target_unexp_stop.29016139750396168377273779385068707261922797041555347687802648729209086000445
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 805932422 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 130 [0x82])
  UVM_INFO @ 805932422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_unexp_stop.50594068781700817519947936089270946220743604476951348641566810527903709462400
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 718754043 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 25 [0x19])
  UVM_INFO @ 718754043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 27 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 22 failures:
- Test i2c_target_hrst has 22 failures.
  - 0.i2c_target_hrst.32687390928720118287644644235867899292268712974837958077313471929290970725264
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10201215427 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10201215427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_hrst.65329714063231573225248909724748097490516588704006302028973584006450852424861
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10612267549 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10612267549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 20 more failures.

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 17 failures:

Test i2c_host_stress_all has 9 failures.

1.i2c_host_stress_all.88873625470843389150770328095161782008872773340819783553887387041150102201806
Line 150, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 12576612886 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4526481

4.i2c_host_stress_all.68006676055793056477367164015450410653311045223033514249875839829110233285209
Line 112, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 92552757407 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @20698

... and 7 more failures.

Test i2c_host_mode_toggle has 8 failures.

4.i2c_host_mode_toggle.115769051822019336420351579378722473468819966626575074040187639715801425866159
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  92494503 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @23550

7.i2c_host_mode_toggle.85316290199353483446654665677629185035908576345471716498697624218594580474103
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 193996334 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @50002

... and 6 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 16 failures:
- Test i2c_target_unexp_stop has 16 failures.
  - 4.i2c_target_unexp_stop.23941879964496641580254714573357368427871980200421744982211015294579333326493
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 491642361 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 491642361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 13.i2c_target_unexp_stop.98631511803007578195564077366254006647372360330490941706951178784222854903721
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  20629347 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  20629347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 14 more failures.

UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.40034484072188452819535519501804629430509803901705879564257685850357761620392
Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3869321001 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3869321001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.63640125385767439768477072163412019721794894310898873836088922208127703370300
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 821797021 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 821797021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 4 failures.

1.i2c_target_stress_all_with_rand_reset.22238161351876562636749630296661459775176322169370414718442764361201671151205
Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 632074151 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 632074151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_all_with_rand_reset.40683388493063667148615876888546124261824329997977409301434223211414289602073
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 269753167 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 269753167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 14 failures:
- Test i2c_target_nack_txstretch has 14 failures.
  - 0.i2c_target_nack_txstretch.94609765170185168160813156270862241925970432112556568036413622620308116670187
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 145314877 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 145314877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_nack_txstretch.54903083027630040003850965540982945367206178239206803080550671458402907673212
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 335642437 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 335642437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 12 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 12 failures:

Test i2c_host_mode_toggle has 12 failures.

5.i2c_host_mode_toggle.103616660713908261236036719064018105539483245532718736103032686633438388286251
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  48372858 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

8.i2c_host_mode_toggle.66636759636005545689312970689082349002868316247481964197283218311061158262595
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  84103372 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 10 more failures.

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 6 failures:
- Test i2c_target_stretch has 6 failures.
  - 4.i2c_target_stretch.7891465163204211383087691588151148438018851271624814170249085021256386642823
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10002845843 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10002845843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.i2c_target_stretch.99710413813898426128375918682332472930568947321427445274247977159871388396808
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10007928644 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10007928644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 5 failures:

Test i2c_target_unexp_stop has 5 failures.

0.i2c_target_unexp_stop.81089453555328830458962138524738919781963727381806785929815205175477610346354
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 596076820 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 596076820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.i2c_target_unexp_stop.26835734313975118436048323480843681954026249968187359053339351918580629584998
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 140617662 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 140617662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 5 failures:
- Test i2c_target_stress_all has 5 failures.
  - 28.i2c_target_stress_all.94826540239715230297433175037453371119733078076681073259910619863279345236070
    Line 98, in log /nightly/current_run/scratch/master/i2c-sim-vcs/28.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 156887618923 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 156887618923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 32.i2c_target_stress_all.42160754199086815072277554212916173998128672878518412588770297312562537583680
    Line 90, in log /nightly/current_run/scratch/master/i2c-sim-vcs/32.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 56393352470 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 56393352470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:

Test i2c_target_glitch has 2 failures.

0.i2c_target_glitch.74557650517756868002075628494433048017850872062913233456982060928527829039463
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 465153578 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 465153578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_glitch.72377327364132630332536795913174715795606565170749696746503524914741491379770
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 2308556296 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 2308556296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 3.i2c_target_stress_all_with_rand_reset.12984697539165707817843373469938810887805949698510129684348554342301947532103
    Line 130, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1598161959 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1598161959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.i2c_target_stress_all_with_rand_reset.24373013440883043557968455581347206892067462022495572304843636777499779806350
    Line 90, in log /nightly/current_run/scratch/master/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2068743815 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2068743815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:

Test i2c_host_mode_toggle has 2 failures.

3.i2c_host_mode_toggle.97587672059460168857475197681531516626475987450660264769648529890619672118569
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log

  UVM_FATAL @ 258813676 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xb5c15894, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 258813676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.i2c_host_mode_toggle.33769890459026865314488437770799655859086748567329007665915598046516672460046
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/19.i2c_host_mode_toggle/latest/run.log

  UVM_FATAL @  28871625 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xd982c814, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  28871625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
- Test i2c_target_tx_stretch_ctrl has 2 failures.
  - 10.i2c_target_tx_stretch_ctrl.99649843420870227484845289330464939276193631288958441401087958398084958520773
    Line 127, in log /nightly/current_run/scratch/master/i2c-sim-vcs/10.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 48.i2c_target_tx_stretch_ctrl.34340847822682414660120939082782382313130363487965103737926075880564298975691
    Line 127, in log /nightly/current_run/scratch/master/i2c-sim-vcs/48.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 2 failures:

Test i2c_host_stress_all has 2 failures.

16.i2c_host_stress_all.38111307726631921660520445603179387932620251204320841173874967665928137422195
Line 155, in log /nightly/current_run/scratch/master/i2c-sim-vcs/16.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 64157603674 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @20382071

33.i2c_host_stress_all.88278032892340650770199539630821558745719906419392871132680878014287770039079
Line 134, in log /nightly/current_run/scratch/master/i2c-sim-vcs/33.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 41902102670 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2471421

UVM_ERROR (cip_base_vseq.sv:840) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test i2c_same_csr_outstanding has 1 failures.
  - 5.i2c_same_csr_outstanding.26888325710673971373692379603189638764523499653930604374566278366412398242052
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @ 133949148 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @ 133949148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[NOA] Null object access has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 12.i2c_host_mode_toggle.77279982516104617942045623246969044945679259045736482221786334056582964997169
    Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/12.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_target_bad_addr has 1 failures.
  - 40.i2c_target_bad_addr.82790201311918985691204269559121440862907778339213757705187081095590996307185
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/40.i2c_target_bad_addr/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```