KEYMGR Simulation Results

Sunday September 28 2025 00:12:59 UTC

GitHub Revision: `c5877ed`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	30.330s	2.884ms	50	50	100.00
V1	random	keymgr_random	37.350s	3.571ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.470s	108.467us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.540s	116.133us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	23.460s	7.817ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	11.330s	3.231ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.310s	53.281us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.540s	116.133us	20	20	100.00
		keymgr_csr_aliasing	11.330s	3.231ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.081m	1.392ms	48	50	96.00
V2	sideload	keymgr_sideload	33.700s	6.989ms	50	50	100.00
		keymgr_sideload_kmac	31.840s	4.056ms	50	50	100.00
		keymgr_sideload_aes	24.060s	4.559ms	50	50	100.00
		keymgr_sideload_otbn	56.610s	7.188ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	19.980s	23.392ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	8.180s	579.462us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	8.180s	290.077us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	59.780s	2.404ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	47.930s	6.398ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	12.830s	457.404us	50	50	100.00
V2	stress_all	keymgr_stress_all	8.546m	56.355ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.180s	85.610us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.410s	24.012us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.210s	117.974us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.210s	117.974us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.470s	108.467us	5	5	100.00
		keymgr_csr_rw	1.540s	116.133us	20	20	100.00
		keymgr_csr_aliasing	11.330s	3.231ms	5	5	100.00
		keymgr_same_csr_outstanding	5.030s	492.230us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.470s	108.467us	5	5	100.00
		keymgr_csr_rw	1.540s	116.133us	20	20	100.00
		keymgr_csr_aliasing	11.330s	3.231ms	5	5	100.00
		keymgr_same_csr_outstanding	5.030s	492.230us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	sec_cm_additional_check	keymgr_sec_cm	12.840s	3.023ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	12.840s	3.023ms	5	5	100.00
		keymgr_tl_intg_err	8.850s	1.013ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.300s	206.867us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.300s	206.867us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.300s	206.867us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.300s	206.867us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.710s	1.594ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	12.840s	3.023ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	12.840s	3.023ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.850s	1.013ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.300s	206.867us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.081m	1.392ms	48	50	96.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	37.350s	3.571ms	50	50	100.00
		keymgr_csr_rw	1.540s	116.133us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	37.350s	3.571ms	50	50	100.00
		keymgr_csr_rw	1.540s	116.133us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	37.350s	3.571ms	50	50	100.00
		keymgr_csr_rw	1.540s	116.133us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	8.180s	579.462us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	47.930s	6.398ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	47.930s	6.398ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	37.350s	3.571ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	31.570s	5.247ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	12.840s	3.023ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	12.840s	3.023ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	12.840s	3.023ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	12.540s	2.828ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	8.180s	579.462us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	12.840s	3.023ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	12.840s	3.023ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	12.840s	3.023ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	12.540s	2.828ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	12.540s	2.828ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	12.840s	3.023ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	12.540s	2.828ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	12.840s	3.023ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	12.540s	2.828ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	24.320s	3.012ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1083	1110	97.57

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.63	99.13	98.22	98.21	100.00	99.01	97.71	91.13

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test keymgr_stress_all_with_rand_reset has 21 failures.
  - 0.keymgr_stress_all_with_rand_reset.84400562586569884207268192860058374423412656148620864090658168928578266494580
    Line 216, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1212094426 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1212094426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.keymgr_stress_all_with_rand_reset.83562013955430726600583122434056136242646863540737458256984763649120921095520
    Line 274, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 411351235 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 411351235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 19 more failures.

UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 6 failures:

Test keymgr_cfg_regwen has 2 failures.

7.keymgr_cfg_regwen.27557875283864761116480756280315599959389767180890987568692984843672717522968
Line 743, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @ 200869618 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 200869618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.keymgr_cfg_regwen.40686144637573575465158537575621377065307556863108082443969657885978401791371
Line 811, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/16.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @ 431884405 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 431884405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 2 failures.

17.keymgr_stress_all.87639598038592493902920463902439634390177082610774630536496215398215601111168
Line 2069, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/17.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 224219108 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 224219108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.keymgr_stress_all.42672996368382304988267223187819000352807531813731746259843318999025549553673
Line 1161, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/26.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 147472671 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 147472671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_hwsw_invalid_input has 1 failures.

22.keymgr_hwsw_invalid_input.87443276472547076905644651886842691390580615820743971417220678286224638656100
Line 141, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/22.keymgr_hwsw_invalid_input/latest/run.log

  UVM_ERROR @   3520112 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   3520112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_kmac_rsp_err has 1 failures.

34.keymgr_kmac_rsp_err.60164549490957596336785059566176906763864587709673387872436183183400717928532
Line 209, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/34.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @   7358427 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   7358427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---