KMAC/MASKED Simulation Results

Sunday September 28 2025 00:12:59 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.634m	33.692ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.830s	263.540us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.580s	124.721us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.090s	1.281ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.880s	1.805ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.060s	67.937us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.580s	124.721us	20	20	100.00
		kmac_csr_aliasing	6.880s	1.805ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.380s	15.830us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.130s	35.536us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.069h	234.015ms	50	50	100.00
V2	burst_write	kmac_burst_write	23.628m	155.143ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	40.384m	382.515ms	5	5	100.00
		kmac_test_vectors_sha3_256	33.617m	1.705s	5	5	100.00
		kmac_test_vectors_sha3_384	26.386m	549.659ms	5	5	100.00
		kmac_test_vectors_sha3_512	17.922m	33.345ms	5	5	100.00
		kmac_test_vectors_shake_128	41.979m	108.335ms	4	5	80.00
		kmac_test_vectors_shake_256	32.978m	361.149ms	5	5	100.00
		kmac_test_vectors_kmac	3.470s	93.796us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.650s	307.326us	5	5	100.00
V2	sideload	kmac_sideload	8.559m	233.923ms	50	50	100.00
V2	app	kmac_app	5.707m	26.690ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.303m	92.202ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.155m	81.763ms	50	50	100.00
V2	error	kmac_error	7.808m	40.726ms	50	50	100.00
V2	key_error	kmac_key_error	19.830s	7.343ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	10.310s	3.376ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	41.020s	1.168ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	34.250s	2.283ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.066m	5.237ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	23.340s	1.785ms	50	50	100.00
V2	stress_all	kmac_stress_all	43.006m	98.962ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.380s	20.664us	50	50	100.00
V2	alert_test	kmac_alert_test	1.330s	177.732us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.490s	269.121us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.490s	269.121us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.830s	263.540us	5	5	100.00
		kmac_csr_rw	1.580s	124.721us	20	20	100.00
		kmac_csr_aliasing	6.880s	1.805ms	5	5	100.00
		kmac_same_csr_outstanding	2.640s	425.910us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.830s	263.540us	5	5	100.00
		kmac_csr_rw	1.580s	124.721us	20	20	100.00
		kmac_csr_aliasing	6.880s	1.805ms	5	5	100.00
		kmac_same_csr_outstanding	2.640s	425.910us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.210s	79.149us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.210s	79.149us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.210s	79.149us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.210s	79.149us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.110s	449.899us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.379m	9.227ms	5	5	100.00
		kmac_tl_intg_err	4.380s	673.774us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.380s	673.774us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	23.340s	1.785ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.634m	33.692ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.559m	233.923ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.210s	79.149us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.379m	9.227ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.379m	9.227ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.379m	9.227ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.634m	33.692ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	23.340s	1.785ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.379m	9.227ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.152m	122.406ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.634m	33.692ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.895m	70.521ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			939	940	99.89

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.03	99.20	94.49	99.89	78.87	97.08	97.83	97.86

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
  • Test kmac_test_vectors_shake_128 has 1 failures.

    • 3.kmac_test_vectors_shake_128.73640020521963244001619256476513044609936207397766731278603594721213049053468
      Line 80, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_128/latest/run.log

        UVM_ERROR @ 105936475 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @ 105936475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---