OTBN Simulation Results

Sunday September 28 2025 00:12:59 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 14.000s 142.465us 0 1 0.00
V1 single_binary otbn_single 45.000s 699.620us 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 5.000s 17.967us 5 5 100.00
V1 csr_rw otbn_csr_rw 4.000s 40.291us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 9.000s 102.423us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 18.836us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 11.000s 42.850us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 4.000s 40.291us 20 20 100.00
otbn_csr_aliasing 4.000s 18.836us 5 5 100.00
V1 mem_walk otbn_mem_walk 1.100m 35.521ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 22.000s 455.365us 5 5 100.00
V1 TOTAL 65 166 39.16
V2 reset_recovery otbn_reset 1.050m 771.143us 0 10 0.00
V2 multi_error otbn_multi_err 53.000s 580.868us 0 1 0.00
V2 back_to_back otbn_multi 3.817m 1.123ms 0 10 0.00
V2 stress_all otbn_stress_all 5.617m 1.194ms 0 10 0.00
V2 lc_escalation otbn_escalate 27.000s 248.150us 15 60 25.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 9.000s 17.536us 1 5 20.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 14.000s 42.461us 0 10 0.00
V2 alert_test otbn_alert_test 6.000s 20.182us 50 50 100.00
V2 intr_test otbn_intr_test 5.000s 22.475us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 9.000s 154.032us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 9.000s 154.032us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 5.000s 17.967us 5 5 100.00
otbn_csr_rw 4.000s 40.291us 20 20 100.00
otbn_csr_aliasing 4.000s 18.836us 5 5 100.00
otbn_same_csr_outstanding 6.000s 32.902us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 5.000s 17.967us 5 5 100.00
otbn_csr_rw 4.000s 40.291us 20 20 100.00
otbn_csr_aliasing 4.000s 18.836us 5 5 100.00
otbn_same_csr_outstanding 6.000s 32.902us 20 20 100.00
V2 TOTAL 156 246 63.41
V2S mem_integrity otbn_imem_err 16.000s 33.822us 1 10 10.00
otbn_dmem_err 15.000s 165.112us 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 18.000s 97.482us 0 5 0.00
otbn_controller_ispr_rdata_err 1.283m 303.894us 0 5 0.00
otbn_mac_bignum_acc_err 12.000s 53.562us 0 5 0.00
otbn_urnd_err 10.000s 31.992us 1 2 50.00
V2S illegal_bus_access otbn_illegal_mem_acc 8.000s 34.526us 5 5 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 9.000s 51.628us 2 2 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 9.000s 40.762us 10 10 100.00
V2S tl_intg_err otbn_sec_cm 14.000s 104.183us 0 5 0.00
otbn_tl_intg_err 41.000s 251.599us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 40.000s 249.278us 19 20 95.00
V2S prim_fsm_check otbn_sec_cm 14.000s 104.183us 0 5 0.00
V2S prim_count_check otbn_sec_cm 14.000s 104.183us 0 5 0.00
V2S sec_cm_mem_scramble otbn_smoke 14.000s 142.465us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 15.000s 165.112us 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 16.000s 33.822us 1 10 10.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 41.000s 251.599us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 27.000s 248.150us 15 60 25.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 16.000s 33.822us 1 10 10.00
otbn_dmem_err 15.000s 165.112us 0 15 0.00
otbn_zero_state_err_urnd 9.000s 17.536us 1 5 20.00
otbn_illegal_mem_acc 8.000s 34.526us 5 5 100.00
otbn_sec_cm 14.000s 104.183us 0 5 0.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 14.000s 104.183us 0 5 0.00
V2S sec_cm_scramble_key_sideload otbn_single 45.000s 699.620us 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 16.000s 33.822us 1 10 10.00
otbn_dmem_err 15.000s 165.112us 0 15 0.00
otbn_zero_state_err_urnd 9.000s 17.536us 1 5 20.00
otbn_illegal_mem_acc 8.000s 34.526us 5 5 100.00
otbn_sec_cm 14.000s 104.183us 0 5 0.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 14.000s 104.183us 0 5 0.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 27.000s 248.150us 15 60 25.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 16.000s 33.822us 1 10 10.00
otbn_dmem_err 15.000s 165.112us 0 15 0.00
otbn_zero_state_err_urnd 9.000s 17.536us 1 5 20.00
otbn_illegal_mem_acc 8.000s 34.526us 5 5 100.00
otbn_sec_cm 14.000s 104.183us 0 5 0.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 14.000s 104.183us 0 5 0.00
V2S sec_cm_data_reg_sw_sca otbn_single 45.000s 699.620us 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 11.000s 23.053us 1 12 8.33
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 10.000s 32.270us 5 5 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 1.333m 208.521us 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 1.333m 208.521us 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 15.000s 211.611us 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 14.000s 104.183us 0 5 0.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 14.000s 104.183us 0 5 0.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 16.000s 60.468us 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 14.000s 104.183us 0 5 0.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 14.000s 104.183us 0 5 0.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 18.000s 170.582us 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 18.000s 170.582us 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 7.000s 9.657us 5 7 71.43
V2S sec_cm_data_mem_sec_wipe otbn_single 45.000s 699.620us 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 45.000s 699.620us 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 45.000s 699.620us 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 3.817m 1.123ms 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 45.000s 699.620us 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 45.000s 699.620us 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 3.067m 755.904us 0 5 0.00
V2S sec_cm_key_sideload otbn_single 45.000s 699.620us 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 14.000s 104.183us 0 5 0.00
V2S TOTAL 69 163 42.33
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 6.267m 2.342ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 290 585 49.57

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
93.59 97.91 72.94 97.08 81.26 52.87 84.62 78.76 94.87

Failure Buckets