c5877ed| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 3.000s | 206.685us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 2.000s | 45.127us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 2.000s | 16.378us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 4.000s | 3.915ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 2.000s | 123.641us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 2.000s | 26.832us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 2.000s | 16.378us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 2.000s | 123.641us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 39.717m | 600.000ms | 31 | 50 | 62.00 |
| V2 | cnt_rollover | cnt_rollover | 1.600m | 2.743ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 2.000s | 22.945us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.822h | 7.911s | 23 | 50 | 46.00 |
| V2 | alert_test | pattgen_alert_test | 2.000s | 12.331us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 2.000s | 14.296us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 4.000s | 1.039ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 4.000s | 1.039ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 2.000s | 45.127us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 2.000s | 16.378us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 123.641us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 2.000s | 69.538us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 2.000s | 45.127us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 2.000s | 16.378us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 123.641us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 2.000s | 69.538us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 294 | 340 | 86.47 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 3.000s | 151.117us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 2.000s | 41.163us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 3.000s | 151.117us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 2.250m | 34.200ms | 1 | 50 | 2.00 |
| V3 | TOTAL | 1 | 50 | 2.00 | |||
| Unmapped tests | pattgen_inactive_level | 4.083m | 10.014ms | 36 | 50 | 72.00 | |
| TOTAL | 461 | 570 | 80.88 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.53 | 100.00 | 100.00 | 100.00 | 98.50 | 96.61 | -- | 96.95 | 89.42 |
UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 49 failures:
0.pattgen_stress_all_with_rand_reset.4417605545459094394370022567021163550713709523635145297328302986740456113045
Line 136, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 452814138 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 452851899 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 452851899 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 453091899 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.4809071522207848393649809946183681276643426900100295409461025375133567152215
Line 203, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2537501995 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 2537512217 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2537512217 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 2537720547 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 47 more failures.
Job timed out after * minutes has 21 failures:
1.pattgen_perf.99211708982018483785068689717344428523082730447269793037448264851015971066212
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_perf/latest/run.log
Job timed out after 60 minutes
2.pattgen_perf.109957044234044028990460177185582122808584399467730941618643487671858308537686
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 10 more failures.
5.pattgen_stress_all.1999116617869784547549752070570687414613545939880941323760500661244686775511
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/5.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
8.pattgen_stress_all.27528209423859616484533890408690918724803737311582422862507784408902479115140
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/8.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 7 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 18 failures:
3.pattgen_stress_all.114448710953935363479210725439334792746541473348055823934525198807693215073765
Line 122, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_stress_all/latest/run.log
UVM_ERROR @ 552507191 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10177
4.pattgen_stress_all.37829998898434531015281859035377977658066139180875214227129693709482456759295
Line 152, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_stress_all/latest/run.log
UVM_ERROR @ 58992400345 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @12541
... and 16 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 7 failures:
13.pattgen_perf.4372886877204842451967505654146095798718232073152823119144875129727493131123
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/13.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.pattgen_perf.68409652127753770694686313975257045630140605465956206472893339480739334807747
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/23.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 2 failures:
1.pattgen_inactive_level.63143692367784607590004748803105020102099310101665917166159982081332009254190
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10017086300 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3a923b90, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 10017086300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.pattgen_inactive_level.63587870378845098173773537347897625216685996359793412912185859911581101703462
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/17.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10021094998 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x2a523fd0, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 10021094998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 2 failures:
10.pattgen_inactive_level.47170945440414463610986706159451223173925426943486261659829080616427548388881
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/10.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10047376527 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x31c101d0, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 10047376527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.pattgen_inactive_level.98881424288695337151632261324217883866776899762671742945531833096427670289741
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/48.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10062766098 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xeaf2b790, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 10062766098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 2 failures:
26.pattgen_inactive_level.82254777801125456638512949606629621102545962949296394241273477794059862328334
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/26.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10277892199 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x382892d0, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
UVM_INFO @ 10277892199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.pattgen_inactive_level.101925480467425773479303496202019878275857578781977546968436852763670570893442
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/36.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10081359391 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc6d1d490, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
UVM_INFO @ 10081359391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 2 failures:
27.pattgen_inactive_level.67195908374868163281984764115625304477487148636191817240154092741008340495384
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/27.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10009248935 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x7aefcdd0, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10009248935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.pattgen_inactive_level.95628449668827598486641738103103370140721102097681173500235735234921898222808
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/45.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10009735436 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x87f3a910, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10009735436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
4.pattgen_inactive_level.80309720951668385233635608317518033120983449008928128449683436893822246208595
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10025753969 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xc8b72cd0, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 10025753969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
12.pattgen_inactive_level.97353045799705668452477421090219903042636413969652173098278962952840196567236
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/12.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10026626017 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x2890a550, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
UVM_INFO @ 10026626017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
28.pattgen_inactive_level.26667758333010356232897491922894798445916086783991855626508602697992945090288
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/28.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10013644166 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xd38c5f50, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10013644166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
32.pattgen_inactive_level.108135507695098798978153661250792861084211056986555841662641673761580606992960
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/32.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10001242905 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc1720a90, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10001242905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
34.pattgen_inactive_level.8585725441836374375063057173209000901738048753887620824951621322158196936125
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/34.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10145262002 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xdbd71550, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10145262002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
40.pattgen_inactive_level.528365298220436223035265494854005178304614770448356601088645626194059854080
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/40.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10064427747 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xbdad190, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10064427747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---