ROM_CTRL/32KB Simulation Results

Sunday September 28 2025 00:12:59 UTC

GitHub Revision: `c5877ed`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.410s	571.739us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	7.830s	299.752us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	6.060s	300.377us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.540s	169.431us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.540s	164.384us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.070s	175.375us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	6.060s	300.377us	20	20	100.00
		rom_ctrl_csr_aliasing	6.540s	164.384us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.150s	171.930us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.250s	129.758us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.550s	175.896us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	28.190s	591.084us	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	7.910s	310.558us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	6.860s	4.973ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	11.720s	189.366us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	11.720s	189.366us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	7.830s	299.752us	5	5	100.00
		rom_ctrl_csr_rw	6.060s	300.377us	20	20	100.00
		rom_ctrl_csr_aliasing	6.540s	164.384us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.440s	149.553us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	7.830s	299.752us	5	5	100.00
		rom_ctrl_csr_rw	6.060s	300.377us	20	20	100.00
		rom_ctrl_csr_aliasing	6.540s	164.384us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.440s	149.553us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.086m	7.764ms	17	20	85.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	29.310s	3.292ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.004m	2.005ms	1	5	20.00
		rom_ctrl_tl_intg_err	1.141m	369.487us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.004m	2.005ms	1	5	20.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.004m	2.005ms	1	5	20.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.086m	7.764ms	17	20	85.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.086m	7.764ms	17	20	85.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.086m	7.764ms	17	20	85.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.086m	7.764ms	17	20	85.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.086m	7.764ms	17	20	85.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.004m	2.005ms	1	5	20.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.004m	2.005ms	1	5	20.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.410s	571.739us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.410s	571.739us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.410s	571.739us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.141m	369.487us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.086m	7.764ms	17	20	85.00
		rom_ctrl_kmac_err_chk	7.910s	310.558us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.086m	7.764ms	17	20	85.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.086m	7.764ms	17	20	85.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.086m	7.764ms	17	20	85.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	29.310s	3.292ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.004m	2.005ms	1	5	20.00
V2S		TOTAL			58	65	89.23
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	7.081m	17.993ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			259	266	97.37

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.00	99.59	98.07	100.00	100.00	99.27	96.80	99.28

Failure Buckets

UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 3 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 3 failures.
  - 3.rom_ctrl_corrupt_sig_fatal_chk.69177067164684754345296143496678870927923598442374100151747394235588536509207
    Line 101, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 2129794480 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 2129794480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.rom_ctrl_corrupt_sig_fatal_chk.113343679097418451348024418468082651029051639207272536591413624057661328116457
    Line 85, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 1329921958 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 1329921958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 2 failures:

Test rom_ctrl_sec_cm has 2 failures.

0.rom_ctrl_sec_cm.31672727405756619038757832386407617569401716435036015490755623655269621604588
Line 180, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 40211942ps failed at 40211942ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 40211942ps failed at 40211942ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

1.rom_ctrl_sec_cm.39817584927170760883817475854621128676898240589872122312339577392512759268860
Line 106, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 3520338ps failed at 3520338ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 3520338ps failed at 3520338ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

Test rom_ctrl_sec_cm has 1 failures.

3.rom_ctrl_sec_cm.113711385170628456905312757818908366679050569141854815217678640752179700471875
Line 114, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  Starting assertion attempts at time 4341335ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
  Starting assertion attempts at time 4341335ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
  Starting assertion attempts at time 4341335ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))

Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:

Test rom_ctrl_sec_cm has 1 failures.

4.rom_ctrl_sec_cm.70461342842210287746566382978016784373708387790105831490544017321355993839297
Line 180, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 36058652ps failed at 36058652ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 36098652ps failed at 36098652ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'