ROM_CTRL/64KB Simulation Results

Sunday September 28 2025 00:12:59 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	10.790s	216.074us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.230s	741.020us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.810s	1.080ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	11.230s	557.876us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.450s	1.067ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.040s	3.862ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.810s	1.080ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.450s	1.067ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	10.820s	1.326ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	11.590s	301.014us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	13.370s	1.384ms	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	1.238m	8.318ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	14.720s	2.111ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	16.320s	1.034ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	16.790s	2.088ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	16.790s	2.088ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.230s	741.020us	5	5	100.00
		rom_ctrl_csr_rw	16.810s	1.080ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.450s	1.067ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.290s	219.786us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.230s	741.020us	5	5	100.00
		rom_ctrl_csr_rw	16.810s	1.080ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.450s	1.067ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.290s	219.786us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.234m	10.677ms	20	20	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.051m	1.665ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	9.929m	16.230ms	2	5	40.00
		rom_ctrl_tl_intg_err	2.328m	387.634us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	9.929m	16.230ms	2	5	40.00
V2S	prim_count_check	rom_ctrl_sec_cm	9.929m	16.230ms	2	5	40.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.234m	10.677ms	20	20	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.234m	10.677ms	20	20	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.234m	10.677ms	20	20	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.234m	10.677ms	20	20	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.234m	10.677ms	20	20	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	9.929m	16.230ms	2	5	40.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	9.929m	16.230ms	2	5	40.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	10.790s	216.074us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	10.790s	216.074us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	10.790s	216.074us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.328m	387.634us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.234m	10.677ms	20	20	100.00
		rom_ctrl_kmac_err_chk	14.720s	2.111ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.234m	10.677ms	20	20	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.234m	10.677ms	20	20	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.234m	10.677ms	20	20	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.051m	1.665ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	9.929m	16.230ms	2	5	40.00
V2S		TOTAL			62	65	95.38
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	6.171m	12.250ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			263	266	98.87

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.14	99.59	98.66	100.00	100.00	99.64	96.80	99.28

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 3 failures:
  • Test rom_ctrl_sec_cm has 3 failures.

    • 0.rom_ctrl_sec_cm.42963746355531235937272085687099623203335131837704053379938048587446823040396
      Line 302, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 39685789ps failed at 39685789ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 39685789ps failed at 39685789ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • 1.rom_ctrl_sec_cm.80459180629670659631108527566910721399697993032773962843595645676946399784770
      Line 105, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 1432944ps failed at 1432944ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 1432944ps failed at 1432944ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • ... and 1 more failures.