RV_TIMER Simulation Results

Sunday September 28 2025 00:12:59 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.600s	408.547us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.630s	41.099us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.660s	25.600us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.910s	248.248us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.770s	42.176us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.100s	55.080us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.660s	25.600us	20	20	100.00
		rv_timer_csr_aliasing	0.770s	42.176us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	4.420s	10.862ms	1	20	5.00
V2	disabled	rv_timer_disabled	2.830s	1.964ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	16.646m	2.751s	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	16.646m	2.751s	10	10	100.00
V2	stress	rv_timer_stress_all	10.390s	6.307ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.940s	21.786us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.650s	14.753us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.990s	610.074us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.990s	610.074us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.630s	41.099us	5	5	100.00
		rv_timer_csr_rw	0.660s	25.600us	20	20	100.00
		rv_timer_csr_aliasing	0.770s	42.176us	5	5	100.00
		rv_timer_same_csr_outstanding	0.790s	72.125us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.630s	41.099us	5	5	100.00
		rv_timer_csr_rw	0.660s	25.600us	20	20	100.00
		rv_timer_csr_aliasing	0.770s	42.176us	5	5	100.00
		rv_timer_same_csr_outstanding	0.790s	72.125us	20	20	100.00
V2		TOTAL			191	210	90.95
V2S	tl_intg_err	rv_timer_sec_cm	1.070s	2.135ms	5	5	100.00
		rv_timer_tl_intg_err	1.170s	279.710us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.170s	279.710us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	20.720s	1.194ms	2	10	20.00
V3	max_value	rv_timer_max	1.100s	77.419us	0	10	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	53.260s	71.080ms	16	20	80.00
V3		TOTAL			18	40	45.00
		TOTAL			309	350	88.29

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.72	100.00	100.00	78.66	--	100.00	96.82	98.82

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 27 failures:
  • Test rv_timer_min has 8 failures.

    • 0.rv_timer_min.95612658598962920333794987613081554087666386908610312840336189710878213384088
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 485660150 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xbce6f04) == 0x1
        UVM_INFO @ 485660150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.rv_timer_min.54568371192485229002986469665567397121148592760678184276128182808011059400681
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_min/latest/run.log

        UVM_FATAL @ 657557815 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe1630104) == 0x1
        UVM_INFO @ 657557815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 6 more failures.

  • Test rv_timer_random_reset has 19 failures.

    • 0.rv_timer_random_reset.30879760573446349899478272646106474313003008174040114078865806194105613396819
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 195307851 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc0ceff04) == 0x1
        UVM_INFO @ 195307851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.rv_timer_random_reset.18756906027853559717313112967595431700052225444082384533482734941237220547166
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 149081537 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd86d0904) == 0x1
        UVM_INFO @ 149081537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 17 more failures.

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 10 failures:
  • Test rv_timer_max has 10 failures.

    • 0.rv_timer_max.108267269269183609760364868468289754184024148014123494388858958602799236040872
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 172083516 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 172083516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.rv_timer_max.73064861542286563354397586505809741318193846220636601006006425823993974076691
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log

        UVM_ERROR @  47171981 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @  47171981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 4 failures:
  • Test rv_timer_stress_all_with_rand_reset has 4 failures.

    • 6.rv_timer_stress_all_with_rand_reset.21208531871031798811235624481978430995300751313738188562224406486778466979288
      Line 140, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/6.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 8521162752 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
        UVM_INFO @ 8521162752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 9.rv_timer_stress_all_with_rand_reset.114964889596015177252430766143812716866528427966838331120501013063562947695682
      Line 314, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/9.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 7707533425 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
        UVM_INFO @ 7707533425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.