SPI_DEVICE/1R1W Simulation Results

Sunday September 28 2025 00:12:59 UTC

GitHub Revision: `c5877ed`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.455m	80.611ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.550s	75.965us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.510s	81.845us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	27.440s	6.939ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.120s	5.221ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.300s	156.007us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.510s	81.845us	20	20	100.00
		spi_device_csr_aliasing	16.120s	5.221ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.930s	12.823us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.710s	698.760us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.200s	18.117us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.100s	3.421us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	15.587us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	12.200s	314.713us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	12.200s	314.713us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	33.640s	16.301ms	50	50	100.00
		spi_device_tpm_sts_read	1.560s	138.511us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	39.890s	35.131ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	45.090s	25.058ms	50	50	100.00
		spi_device_flash_all	7.077m	146.865ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	36.240s	15.214ms	50	50	100.00
		spi_device_flash_all	7.077m	146.865ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	36.240s	15.214ms	50	50	100.00
		spi_device_flash_all	7.077m	146.865ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.077m	146.865ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	26.210s	14.218ms	50	50	100.00
		spi_device_flash_all	7.077m	146.865ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	26.210s	14.218ms	50	50	100.00
		spi_device_flash_all	7.077m	146.865ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	26.210s	14.218ms	50	50	100.00
		spi_device_flash_all	7.077m	146.865ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	26.210s	14.218ms	50	50	100.00
		spi_device_flash_all	7.077m	146.865ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	26.210s	14.218ms	50	50	100.00
		spi_device_flash_all	7.077m	146.865ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	29.990s	30.762ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.334m	12.986ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.334m	12.986ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.334m	12.986ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	42.040s	4.210ms	50	50	100.00
		spi_device_read_buffer_direct	16.930s	2.669ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.334m	12.986ms	50	50	100.00
		spi_device_flash_all	7.077m	146.865ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.077m	146.865ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.077m	146.865ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	16.300s	1.479ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	16.300s	1.479ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.455m	80.611ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	6.615m	118.852ms	50	50	100.00
V2	stress_all	spi_device_stress_all	15.577m	275.467ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.150s	14.852us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.040s	63.004us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.340s	658.270us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.340s	658.270us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.550s	75.965us	5	5	100.00
		spi_device_csr_rw	2.510s	81.845us	20	20	100.00
		spi_device_csr_aliasing	16.120s	5.221ms	5	5	100.00
		spi_device_same_csr_outstanding	3.710s	771.923us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.550s	75.965us	5	5	100.00
		spi_device_csr_rw	2.510s	81.845us	20	20	100.00
		spi_device_csr_aliasing	16.120s	5.221ms	5	5	100.00
		spi_device_same_csr_outstanding	3.710s	771.923us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	1.770s	131.917us	5	5	100.00
		spi_device_tl_intg_err	19.070s	2.193ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	19.070s	2.193ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.632m	361.032ms	50	50	100.00
		TOTAL			1130	1151	98.18

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.62	99.11	96.56	71.19	89.36	98.40	94.43	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.101553056241804963774683516949326312920633911266657163833670956879734750360919
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1154928 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[109])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1154928 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1154928 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1005])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.49454153804472790514309275035777338539657628303638524967609708926192299325160
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4790441 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[106])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4790441 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4790441 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1002])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])

has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.111875144380294178054957541343909232357574714494057524781259048984723818120305
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @  13120370 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe5729f [111001010111001010011111] vs 0x0 [0])
  UVM_ERROR @  13203370 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x310cad [1100010000110010101101] vs 0x0 [0])
  UVM_ERROR @  13205370 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa07c84 [101000000111110010000100] vs 0x0 [0])
  UVM_ERROR @  13241370 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xafe0e [10101111111000001110] vs 0x0 [0])
  UVM_ERROR @  13322370 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc46163 [110001000110000101100011] vs 0x0 [0])