SPI_DEVICE/2P Simulation Results

Sunday September 28 2025 00:12:59 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.606m	64.240ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.380s	20.644us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.380s	140.491us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.630s	10.029ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.670s	1.230ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.250s	158.853us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.380s	140.491us	20	20	100.00
		spi_device_csr_aliasing	14.670s	1.230ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.810s	65.406us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.900s	419.288us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.220s	21.732us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.480s	104.135us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.150s	41.037us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	4.430s	96.079us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	4.430s	96.079us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	28.750s	46.656ms	50	50	100.00
		spi_device_tpm_sts_read	1.410s	187.742us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	46.930s	30.059ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	52.730s	36.145ms	50	50	100.00
		spi_device_flash_all	5.333m	341.077ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	21.310s	29.872ms	50	50	100.00
		spi_device_flash_all	5.333m	341.077ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	21.310s	29.872ms	50	50	100.00
		spi_device_flash_all	5.333m	341.077ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.333m	341.077ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	29.670s	5.428ms	50	50	100.00
		spi_device_flash_all	5.333m	341.077ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	29.670s	5.428ms	50	50	100.00
		spi_device_flash_all	5.333m	341.077ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	29.670s	5.428ms	50	50	100.00
		spi_device_flash_all	5.333m	341.077ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	29.670s	5.428ms	50	50	100.00
		spi_device_flash_all	5.333m	341.077ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	29.670s	5.428ms	50	50	100.00
		spi_device_flash_all	5.333m	341.077ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	33.860s	83.355ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.799m	11.651ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.799m	11.651ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.799m	11.651ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	48.690s	8.415ms	50	50	100.00
		spi_device_read_buffer_direct	14.300s	1.486ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.799m	11.651ms	50	50	100.00
		spi_device_flash_all	5.333m	341.077ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.333m	341.077ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.333m	341.077ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	19.650s	1.769ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	19.650s	1.769ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.606m	64.240ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.795m	76.812ms	50	50	100.00
V2	stress_all	spi_device_stress_all	10.369m	150.185ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.150s	67.544us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.070s	15.382us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.610s	207.839us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.610s	207.839us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.380s	20.644us	5	5	100.00
		spi_device_csr_rw	2.380s	140.491us	20	20	100.00
		spi_device_csr_aliasing	14.670s	1.230ms	5	5	100.00
		spi_device_same_csr_outstanding	3.600s	72.332us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.380s	20.644us	5	5	100.00
		spi_device_csr_rw	2.380s	140.491us	20	20	100.00
		spi_device_csr_aliasing	14.670s	1.230ms	5	5	100.00
		spi_device_same_csr_outstanding	3.600s	72.332us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.720s	633.650us	5	5	100.00
		spi_device_tl_intg_err	16.860s	856.673us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.860s	856.673us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	4.787m	554.269ms	50	50	100.00
		TOTAL			1151	1151	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.16	99.17	96.66	74.78	89.36	98.49	94.41	99.26