SPI_HOST Simulation Results

Sunday September 28 2025 00:12:59 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	2.033m	11.687ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	20.528us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	49.282us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	265.772us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	24.093us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	82.677us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	49.282us	20	20	100.00
		spi_host_csr_aliasing	2.000s	24.093us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	76.956us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	24.761us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	36.000s	23.257us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	39.000s	263.041us	50	50	100.00
		spi_host_error_cmd	32.000s	42.318us	50	50	100.00
		spi_host_event	11.383m	23.721ms	50	50	100.00
V2	clock_rate	spi_host_speed	38.000s	190.796us	50	50	100.00
V2	speed	spi_host_speed	38.000s	190.796us	50	50	100.00
V2	chip_select_timing	spi_host_speed	38.000s	190.796us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	10.533m	68.283ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	26.259us	50	50	100.00
V2	cpol_cpha	spi_host_speed	38.000s	190.796us	50	50	100.00
V2	full_cycle	spi_host_speed	38.000s	190.796us	50	50	100.00
V2	duplex	spi_host_smoke	2.033m	11.687ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	2.033m	11.687ms	50	50	100.00
V2	stress_all	spi_host_stress_all	2.300m	14.330ms	50	50	100.00
V2	spien	spi_host_spien	5.933m	160.190ms	50	50	100.00
V2	stall	spi_host_status_stall	19.667m	182.886ms	50	50	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	15.000s	1.907ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	39.000s	263.041us	50	50	100.00
V2	alert_test	spi_host_alert_test	2.000s	15.349us	50	50	100.00
V2	intr_test	spi_host_intr_test	2.000s	39.773us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	3.000s	154.217us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	3.000s	154.217us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	20.528us	5	5	100.00
		spi_host_csr_rw	2.000s	49.282us	20	20	100.00
		spi_host_csr_aliasing	2.000s	24.093us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	27.765us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	20.528us	5	5	100.00
		spi_host_csr_rw	2.000s	49.282us	20	20	100.00
		spi_host_csr_aliasing	2.000s	24.093us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	27.765us	20	20	100.00
V2		TOTAL			690	690	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	232.329us	20	20	100.00
		spi_host_sec_cm	2.000s	139.505us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	232.329us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	9.133m	15.249ms	10	10	100.00
		TOTAL			840	840	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.09	96.82	93.35	98.69	94.25	73.07	100.00	95.21	90.42