SRAM_CTRL/MAIN Simulation Results

Sunday September 28 2025 00:12:59 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.451m	797.248us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.110s	39.892us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.060s	15.005us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.780s	708.819us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.140s	59.768us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.560s	406.706us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.060s	15.005us	20	20	100.00
		sram_ctrl_csr_aliasing	1.140s	59.768us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.895m	55.302ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.972m	50.245ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	20.241m	243.285ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.499m	11.643ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	48.313m	1.897s	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.259m	26.814ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.942m	64.490ms	50	50	100.00
V2	executable	sram_ctrl_executable	28.370m	112.899ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.419m	2.538ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.999m	106.520ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.678m	3.190ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.787m	6.023ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.804m	936.530us	50	50	100.00
V2	regwen	sram_ctrl_regwen	22.379m	20.172ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.390s	1.353ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.645h	2.134s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.070s	23.731us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.720s	469.979us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.720s	469.979us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.110s	39.892us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	15.005us	20	20	100.00
		sram_ctrl_csr_aliasing	1.140s	59.768us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.200s	27.221us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.110s	39.892us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	15.005us	20	20	100.00
		sram_ctrl_csr_aliasing	1.140s	59.768us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.200s	27.221us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.059m	30.832ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.010s	6.056us	0	5	0.00
		sram_ctrl_tl_intg_err	3.630s	1.322ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.010s	6.056us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.630s	1.322ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	22.379m	20.172ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	22.379m	20.172ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.060s	15.005us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	28.370m	112.899ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	28.370m	112.899ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	28.370m	112.899ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.942m	64.490ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	9.250s	2.902ms	43	50	86.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.059m	30.832ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	8.910s	2.438ms	40	50	80.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.451m	797.248us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.451m	797.248us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	28.370m	112.899ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.010s	6.056us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.942m	64.490ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.010s	6.056us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.010s	6.056us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.451m	797.248us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.010s	6.056us	0	5	0.00
V2S		TOTAL			123	145	84.83
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.969m	2.524ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1168	1190	98.15

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.66	99.11	92.90	85.46	100.00	98.02	95.83	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 10 failures:

  • Test sram_ctrl_readback_err has 10 failures.

    • 5.sram_ctrl_readback_err.815013104995248698385286695347986884228024716455631211189367563435454958929
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/5.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 662657193 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2b) != exp (0x2f)
        UVM_INFO @ 662657193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 14.sram_ctrl_readback_err.88318319609366600275938149306033297210475905212934499817429987285828617946282
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/14.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2527495563 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3f) != exp (0x0)
        UVM_INFO @ 2527495563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• Offending 'reqfifo_rvalid' has 7 failures:

  • Test sram_ctrl_mubi_enc_err has 7 failures.

    • 6.sram_ctrl_mubi_enc_err.12214659306155376984493172922285728131916564622351721773316600434090222612705
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/6.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 678914924 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 678914924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.sram_ctrl_mubi_enc_err.14956360367583979053326856397444816794451232065324329229544361267772460687094
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2635826093 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2635826093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 1.sram_ctrl_sec_cm.64432485614012914925715721577513514138007251007979946092331245877099373278406
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6056322 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6056322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.110355543443204541508085993393591232209507240561139735997939286460108892414348
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1956101 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1956101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.2476021120531421857241396328384317924221020707323760463703194857236071561451
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   6714616 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   6714616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 4.sram_ctrl_sec_cm.49384577950665478857382982624755921207007603021590312251402459193955274314519
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 1918591ps failed at 1918591ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respOpcode_A: started at 1938591ps failed at 1938591ps
            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'