SRAM_CTRL/RET Simulation Results

Sunday September 28 2025 00:12:59 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.307m	668.711us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.010s	46.886us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.050s	14.695us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.170s	273.732us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.020s	37.780us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	9.280s	10.005ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.050s	14.695us	20	20	100.00
		sram_ctrl_csr_aliasing	1.020s	37.780us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.550s	2.721ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	7.450s	2.251ms	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	29.130m	39.312ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.534m	14.724ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.291m	13.931ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.829m	10.242ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	12.370s	3.499ms	50	50	100.00
V2	executable	sram_ctrl_executable	21.586m	72.335ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.728m	744.843us	50	50	100.00
		sram_ctrl_partial_access_b2b	8.262m	21.304ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.550m	254.810us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.598m	163.521us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.693m	668.490us	50	50	100.00
V2	regwen	sram_ctrl_regwen	22.545m	17.330ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.170s	117.649us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.346h	20.380ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.060s	27.143us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.650s	482.053us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.650s	482.053us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.010s	46.886us	5	5	100.00
		sram_ctrl_csr_rw	1.050s	14.695us	20	20	100.00
		sram_ctrl_csr_aliasing	1.020s	37.780us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.260s	217.339us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.010s	46.886us	5	5	100.00
		sram_ctrl_csr_rw	1.050s	14.695us	20	20	100.00
		sram_ctrl_csr_aliasing	1.020s	37.780us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.260s	217.339us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.770s	2.444ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.200s	7.764us	0	5	0.00
		sram_ctrl_tl_intg_err	3.360s	3.279ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.200s	7.764us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.360s	3.279ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	22.545m	17.330ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	22.545m	17.330ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.050s	14.695us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	21.586m	72.335ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	21.586m	72.335ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	21.586m	72.335ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	12.370s	3.499ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.620s	44.679us	48	50	96.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.770s	2.444ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.630s	410.652us	42	50	84.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.307m	668.711us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.307m	668.711us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	21.586m	72.335ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.200s	7.764us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	12.370s	3.499ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.200s	7.764us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.200s	7.764us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.307m	668.711us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.200s	7.764us	0	5	0.00
V2S		TOTAL			130	145	89.66
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	10.435m	11.105ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1173	1190	98.57

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.64	99.07	92.90	85.37	100.00	97.98	95.79	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 8 failures:

  • Test sram_ctrl_readback_err has 8 failures.

    • 1.sram_ctrl_readback_err.89009406619897844880829572692149661732285797182338195362859813566107194293155
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  76590657 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4a) != exp (0x4e)
        UVM_INFO @  76590657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 8.sram_ctrl_readback_err.41142310981688787142481201597758977425722146051529150358103303390742328220067
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/8.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  87558904 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x54) != exp (0x9)
        UVM_INFO @  87558904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 6 more failures.

• Offending '(depth_o <= *'(Depth))' has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 0.sram_ctrl_sec_cm.28901984105278733802136783149984375165478566731498224282464027470750443018174
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   4070400 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   4070400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_sec_cm.112517154274575834408410529171932720355844112432485385066854944922719713256905
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @    961973 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @    961973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 1.sram_ctrl_sec_cm.33496536427741278377180578550194080613327225450700110236696479772776808897171
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4831892 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4831892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.89751389014994063756545128383033230842751893437019509177514040243818718603903
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7244478 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7244478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'reqfifo_rvalid' has 2 failures:

  • Test sram_ctrl_mubi_enc_err has 2 failures.

    • 12.sram_ctrl_mubi_enc_err.32758684408812273020338729392353383810625053843144411197773238862594751840630
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 148333008 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 148333008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 35.sram_ctrl_mubi_enc_err.44105563409612799254066542858988181877799130846448198104436683511364548963272
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 290106294 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 290106294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 4.sram_ctrl_csr_mem_rw_with_rand_reset.513359695712813728702343875864173025591329602108515483920297135908449653788
      Line 93, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_FATAL @ 10005150121 ps: (sram_ctrl_base_vseq.sv:168) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
        UVM_INFO @ 10005150121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 25.sram_ctrl_stress_all_with_rand_reset.2335535040951717304460989128829551515656413262653998009020568304848633671146
      Line 211, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1707070774 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1707070774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---