ADC_CTRL Simulation Results

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: `7302728`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	22.880s	5.985ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.200s	722.578us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.650s	570.433us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.060m	48.479ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.580s	915.358us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	3.360s	578.883us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.650s	570.433us	20	20	100.00
		adc_ctrl_csr_aliasing	5.580s	915.358us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.578m	492.111ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	21.157m	489.595ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.420m	486.520ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.526m	491.021ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	26.855m	687.919ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	25.932m	605.222ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.953m	600.000ms	47	50	94.00
V2	clock_gating	adc_ctrl_clock_gating	20.755m	512.589ms	33	50	66.00
V2	poweron_counter	adc_ctrl_poweron_counter	16.380s	4.620ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.852m	46.485ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	6.976m	124.303ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	59.626m	10.000s	45	50	90.00
V2	alert_test	adc_ctrl_alert_test	2.470s	502.467us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	2.590s	497.855us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.100s	460.588us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.100s	460.588us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.200s	722.578us	5	5	100.00
		adc_ctrl_csr_rw	2.650s	570.433us	20	20	100.00
		adc_ctrl_csr_aliasing	5.580s	915.358us	5	5	100.00
		adc_ctrl_same_csr_outstanding	20.230s	3.613ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.200s	722.578us	5	5	100.00
		adc_ctrl_csr_rw	2.650s	570.433us	20	20	100.00
		adc_ctrl_csr_aliasing	5.580s	915.358us	5	5	100.00
		adc_ctrl_same_csr_outstanding	20.230s	3.613ms	20	20	100.00
V2		TOTAL			715	740	96.62
V2S	tl_intg_err	adc_ctrl_sec_cm	24.600s	7.446ms	5	5	100.00
		adc_ctrl_tl_intg_err	27.510s	8.265ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	27.510s	8.265ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	50.330s	102.413ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			893	920	97.07

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.41	99.05	96.03	100.00	100.00	98.64	95.95	92.18

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 18 failures:

Test adc_ctrl_clock_gating has 12 failures.

7.adc_ctrl_clock_gating.12298814746382344119067222262533001597000443203237078607480184769377216414284
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest/run.log

  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.adc_ctrl_clock_gating.59813877316083683774808088083235590793001001363572515968969772655972691103880
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/11.adc_ctrl_clock_gating/latest/run.log

  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

Test adc_ctrl_stress_all has 4 failures.

9.adc_ctrl_stress_all.8948382204608412705646435337331936682634696352916809446764648023321178919814
Line 149, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.adc_ctrl_stress_all.24145360621687849396878000415704011044610510368218129179235091870864263261964
Line 162, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test adc_ctrl_filters_both has 2 failures.

15.adc_ctrl_filters_both.99917275507074000152376756862535058056125162197016944633162268768596998515192
Line 180, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/15.adc_ctrl_filters_both/latest/run.log

  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.adc_ctrl_filters_both.78579143253670395487523389597308153380673213425939594432583310741278077536190
Line 180, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/41.adc_ctrl_filters_both/latest/run.log

  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 7 failures:

Test adc_ctrl_stress_all_with_rand_reset has 2 failures.

13.adc_ctrl_stress_all_with_rand_reset.89192573842519709988912284456639010207616964244241614746011686891818673377506
Line 205, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8993597543 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 8993597543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.adc_ctrl_stress_all_with_rand_reset.5472799443740041309546934124463730780013965381092221339174885682180526244291
Line 154, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 22146760792 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 22146760792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_clock_gating has 4 failures.

14.adc_ctrl_clock_gating.103393254190190203217725182811671202285336772807792393744352354661436019982224
Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/14.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 163354203646 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 163354203646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.adc_ctrl_clock_gating.69152861138402479503676701241532038947940942668011034860457269839348020850276
Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/21.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 164571348050 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 164571348050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test adc_ctrl_stress_all has 1 failures.

24.adc_ctrl_stress_all.32319526419980153297223363630394136047558925743567409442519413927808384469478
Line 149, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 2079741588 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 2079741588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 2 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 9.adc_ctrl_filters_both.107121729796636946523964884540130261408425328862257944095035084001700737828878
    Line 180, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_filters_both/latest/run.log
```
  UVM_ERROR @ 517527089782 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 517527089782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test adc_ctrl_clock_gating has 1 failures.
  - 37.adc_ctrl_clock_gating.94961855199426049384149811109993331093666380757919850569198838854244964560675
    Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/37.adc_ctrl_clock_gating/latest/run.log
```
  UVM_ERROR @ 196699512190 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 196699512190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```