AES/MASKED Simulation Results

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: `7302728`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	123.717us	1	1	100.00
V1	smoke	aes_smoke	29.000s	4.742ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	66.406us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	88.808us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	1.202ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	91.596us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	101.696us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	88.808us	20	20	100.00
		aes_csr_aliasing	3.000s	91.596us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	29.000s	4.742ms	50	50	100.00
		aes_config_error	9.000s	465.539us	50	50	100.00
		aes_stress	24.000s	1.703ms	50	50	100.00
V2	key_length	aes_smoke	29.000s	4.742ms	50	50	100.00
		aes_config_error	9.000s	465.539us	50	50	100.00
		aes_stress	24.000s	1.703ms	50	50	100.00
V2	back2back	aes_stress	24.000s	1.703ms	50	50	100.00
		aes_b2b	27.000s	704.928us	50	50	100.00
V2	backpressure	aes_stress	24.000s	1.703ms	50	50	100.00
V2	multi_message	aes_smoke	29.000s	4.742ms	50	50	100.00
		aes_config_error	9.000s	465.539us	50	50	100.00
		aes_stress	24.000s	1.703ms	50	50	100.00
		aes_alert_reset	20.000s	1.683ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	243.828us	50	50	100.00
		aes_config_error	9.000s	465.539us	50	50	100.00
		aes_alert_reset	20.000s	1.683ms	50	50	100.00
V2	trigger_clear_test	aes_clear	48.000s	4.877ms	49	50	98.00
V2	nist_test_vectors	aes_nist_vectors	9.000s	405.126us	1	1	100.00
V2	reset_recovery	aes_alert_reset	20.000s	1.683ms	50	50	100.00
V2	stress	aes_stress	24.000s	1.703ms	50	50	100.00
V2	sideload	aes_stress	24.000s	1.703ms	50	50	100.00
		aes_sideload	7.000s	152.904us	50	50	100.00
V2	deinitialization	aes_deinit	32.000s	3.002ms	50	50	100.00
V2	stress_all	aes_stress_all	54.000s	5.207ms	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	63.039us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	1.640ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	1.640ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	66.406us	5	5	100.00
		aes_csr_rw	3.000s	88.808us	20	20	100.00
		aes_csr_aliasing	3.000s	91.596us	5	5	100.00
		aes_same_csr_outstanding	3.000s	71.761us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	66.406us	5	5	100.00
		aes_csr_rw	3.000s	88.808us	20	20	100.00
		aes_csr_aliasing	3.000s	91.596us	5	5	100.00
		aes_same_csr_outstanding	3.000s	71.761us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	14.000s	271.932us	50	50	100.00
V2S	fault_inject	aes_fi	13.000s	1.391ms	50	50	100.00
		aes_control_fi	43.000s	10.006ms	281	300	93.67
		aes_cipher_fi	59.000s	10.022ms	340	350	97.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	106.612us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	106.612us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	106.612us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	106.612us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	3.000s	438.808us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	12.000s	1.677ms	5	5	100.00
		aes_tl_intg_err	4.000s	195.534us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	4.000s	195.534us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	20.000s	1.683ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	106.612us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	29.000s	4.742ms	50	50	100.00
		aes_stress	24.000s	1.703ms	50	50	100.00
		aes_alert_reset	20.000s	1.683ms	50	50	100.00
		aes_core_fi	1.033m	10.452ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	106.612us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	347.585us	50	50	100.00
		aes_stress	24.000s	1.703ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	24.000s	1.703ms	50	50	100.00
		aes_sideload	7.000s	152.904us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	347.585us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	347.585us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	347.585us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	347.585us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	347.585us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	24.000s	1.703ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	24.000s	1.703ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	13.000s	1.391ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	13.000s	1.391ms	50	50	100.00
		aes_control_fi	43.000s	10.006ms	281	300	93.67
		aes_cipher_fi	59.000s	10.022ms	340	350	97.14
		aes_ctr_fi	9.000s	840.170us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	13.000s	1.391ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	13.000s	1.391ms	50	50	100.00
		aes_control_fi	43.000s	10.006ms	281	300	93.67
		aes_cipher_fi	59.000s	10.022ms	340	350	97.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	59.000s	10.022ms	340	350	97.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	13.000s	1.391ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	13.000s	1.391ms	50	50	100.00
		aes_control_fi	43.000s	10.006ms	281	300	93.67
		aes_ctr_fi	9.000s	840.170us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	13.000s	1.391ms	50	50	100.00
		aes_control_fi	43.000s	10.006ms	281	300	93.67
		aes_cipher_fi	59.000s	10.022ms	340	350	97.14
		aes_ctr_fi	9.000s	840.170us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	20.000s	1.683ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	13.000s	1.391ms	50	50	100.00
		aes_control_fi	43.000s	10.006ms	281	300	93.67
		aes_cipher_fi	59.000s	10.022ms	340	350	97.14
		aes_ctr_fi	9.000s	840.170us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	13.000s	1.391ms	50	50	100.00
		aes_control_fi	43.000s	10.006ms	281	300	93.67
		aes_cipher_fi	59.000s	10.022ms	340	350	97.14
		aes_ctr_fi	9.000s	840.170us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	13.000s	1.391ms	50	50	100.00
		aes_control_fi	43.000s	10.006ms	281	300	93.67
		aes_ctr_fi	9.000s	840.170us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	13.000s	1.391ms	50	50	100.00
		aes_control_fi	43.000s	10.006ms	281	300	93.67
		aes_cipher_fi	59.000s	10.022ms	340	350	97.14
V2S		TOTAL			954	985	96.85
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	37.000s	724.835us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1560	1602	97.38

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.39	98.64	96.54	99.45	95.48	98.07	100.00	98.36	98.19

Failure Buckets

Job timed out after * minutes has 11 failures:
- Test aes_control_fi has 11 failures.
  - 0.aes_control_fi.50004338305428675851046995813328295027160413786878661450693055437744632633325
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 32.aes_control_fi.84346425085067604458384365606377128062610468451887373874911325967131884650180
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/32.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 9 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 15.aes_cipher_fi.18092125856742612676396968229120258901675841374551763750636636617005104148056
    Line 133, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/15.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011441514 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011441514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 90.aes_cipher_fi.99476651675059708166562462648469525385114632358574430094593091272919804202073
    Line 142, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/90.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006850956 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006850956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.5356065949497337716893794575723982475326758569939610994004649578053148220011
Line 1031, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 724835479 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 724835479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.62688805616926821402935206586059796981507807419970547011886482023536687476526
Line 191, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 128096836 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 128096836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 5.aes_control_fi.87399018864284385973183409363049888121052560205792195442476804659265659639234
    Line 142, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10020350057 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020350057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 129.aes_control_fi.95009688818443536722149962151592357855493536170682854419307328532146805701321
    Line 139, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/129.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10017568976 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017568976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 5.aes_stress_all_with_rand_reset.96734100998969216621538927080957866457889923488319663186464420872737778488587
    Line 367, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 913087536 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 913087536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.aes_stress_all_with_rand_reset.42985711732476438941422759052741644005847632565663650983894357295644922079832
    Line 790, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 7567419660 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 7567419660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 13.aes_core_fi.36040642910128659352275964802104475858358672434826453510209718112188492148707
    Line 143, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/13.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10451959808 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10451959808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 25.aes_core_fi.84115745554782960905685711135120225647334685446522674319055846919749402713418
    Line 143, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/25.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10039336602 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10039336602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.93781566626269134161919119871778689823318787505871022751188053770052240442360
    Line 679, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 787364263 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 787364263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_scoreboard.sv:611) scoreboard [scoreboard] # * has 1 failures:
- Test aes_clear has 1 failures.
  - 26.aes_clear.57828965244557658816567496989421150722209328789819898794119231608251578252787
    Line 23835, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/26.aes_clear/latest/run.log
```
  UVM_FATAL @  59123234 ps: (aes_scoreboard.sv:611) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 3
           TEST FAILED MESSAGES DID NOT MATCH

                 0 3f 	 5b 	 54 	 0
                 1 fb 	 ed 	 9f 	 0
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_control_fi has 1 failures.
  - 71.aes_control_fi.5672430773600851828635400029097671848004833220972460101031993644093645618343
    Line 136, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/71.aes_control_fi/latest/run.log
```
  UVM_ERROR @  63692965 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  63692965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```