AES/UNMASKED Simulation Results

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: `7302728`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	58.368us	1	1	100.00
V1	smoke	aes_smoke	3.000s	76.021us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	60.311us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	104.123us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	7.000s	988.815us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	534.161us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	85.817us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	104.123us	20	20	100.00
		aes_csr_aliasing	3.000s	534.161us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	3.000s	76.021us	50	50	100.00
		aes_config_error	10.000s	1.131ms	50	50	100.00
		aes_stress	4.000s	404.607us	50	50	100.00
V2	key_length	aes_smoke	3.000s	76.021us	50	50	100.00
		aes_config_error	10.000s	1.131ms	50	50	100.00
		aes_stress	4.000s	404.607us	50	50	100.00
V2	back2back	aes_stress	4.000s	404.607us	50	50	100.00
		aes_b2b	7.000s	153.390us	50	50	100.00
V2	backpressure	aes_stress	4.000s	404.607us	50	50	100.00
V2	multi_message	aes_smoke	3.000s	76.021us	50	50	100.00
		aes_config_error	10.000s	1.131ms	50	50	100.00
		aes_stress	4.000s	404.607us	50	50	100.00
		aes_alert_reset	4.000s	178.796us	50	50	100.00
V2	failure_test	aes_man_cfg_err	3.000s	340.679us	50	50	100.00
		aes_config_error	10.000s	1.131ms	50	50	100.00
		aes_alert_reset	4.000s	178.796us	50	50	100.00
V2	trigger_clear_test	aes_clear	4.000s	114.333us	49	50	98.00
V2	nist_test_vectors	aes_nist_vectors	4.000s	117.373us	1	1	100.00
V2	reset_recovery	aes_alert_reset	4.000s	178.796us	50	50	100.00
V2	stress	aes_stress	4.000s	404.607us	50	50	100.00
V2	sideload	aes_stress	4.000s	404.607us	50	50	100.00
		aes_sideload	4.000s	378.276us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	276.820us	50	50	100.00
V2	stress_all	aes_stress_all	18.000s	1.405ms	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	80.361us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	82.810us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	82.810us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	60.311us	5	5	100.00
		aes_csr_rw	3.000s	104.123us	20	20	100.00
		aes_csr_aliasing	3.000s	534.161us	5	5	100.00
		aes_same_csr_outstanding	3.000s	461.416us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	60.311us	5	5	100.00
		aes_csr_rw	3.000s	104.123us	20	20	100.00
		aes_csr_aliasing	3.000s	534.161us	5	5	100.00
		aes_same_csr_outstanding	3.000s	461.416us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	4.000s	401.493us	50	50	100.00
V2S	fault_inject	aes_fi	3.000s	191.199us	50	50	100.00
		aes_control_fi	36.000s	10.003ms	278	300	92.67
		aes_cipher_fi	31.000s	10.017ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	231.281us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	231.281us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	231.281us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	231.281us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	3.000s	251.044us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	4.000s	2.366ms	5	5	100.00
		aes_tl_intg_err	4.000s	437.467us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	4.000s	437.467us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	4.000s	178.796us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	231.281us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	3.000s	76.021us	50	50	100.00
		aes_stress	4.000s	404.607us	50	50	100.00
		aes_alert_reset	4.000s	178.796us	50	50	100.00
		aes_core_fi	1.900m	10.026ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	231.281us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	116.751us	50	50	100.00
		aes_stress	4.000s	404.607us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	4.000s	404.607us	50	50	100.00
		aes_sideload	4.000s	378.276us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	116.751us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	116.751us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	116.751us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	116.751us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	116.751us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.000s	404.607us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	4.000s	404.607us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	3.000s	191.199us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	3.000s	191.199us	50	50	100.00
		aes_control_fi	36.000s	10.003ms	278	300	92.67
		aes_cipher_fi	31.000s	10.017ms	338	350	96.57
		aes_ctr_fi	3.000s	70.202us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	3.000s	191.199us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	3.000s	191.199us	50	50	100.00
		aes_control_fi	36.000s	10.003ms	278	300	92.67
		aes_cipher_fi	31.000s	10.017ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	31.000s	10.017ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	3.000s	191.199us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	3.000s	191.199us	50	50	100.00
		aes_control_fi	36.000s	10.003ms	278	300	92.67
		aes_ctr_fi	3.000s	70.202us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	3.000s	191.199us	50	50	100.00
		aes_control_fi	36.000s	10.003ms	278	300	92.67
		aes_cipher_fi	31.000s	10.017ms	338	350	96.57
		aes_ctr_fi	3.000s	70.202us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	4.000s	178.796us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	3.000s	191.199us	50	50	100.00
		aes_control_fi	36.000s	10.003ms	278	300	92.67
		aes_cipher_fi	31.000s	10.017ms	338	350	96.57
		aes_ctr_fi	3.000s	70.202us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	3.000s	191.199us	50	50	100.00
		aes_control_fi	36.000s	10.003ms	278	300	92.67
		aes_cipher_fi	31.000s	10.017ms	338	350	96.57
		aes_ctr_fi	3.000s	70.202us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	3.000s	191.199us	50	50	100.00
		aes_control_fi	36.000s	10.003ms	278	300	92.67
		aes_ctr_fi	3.000s	70.202us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	3.000s	191.199us	50	50	100.00
		aes_control_fi	36.000s	10.003ms	278	300	92.67
		aes_cipher_fi	31.000s	10.017ms	338	350	96.57
V2S		TOTAL			949	985	96.35
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	20.000s	3.382ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1555	1602	97.07

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.25	97.66	94.71	98.78	93.26	98.07	91.85	97.88	98.79

Failure Buckets

Job timed out after * minutes has 15 failures:
- Test aes_cipher_fi has 5 failures.
  - 18.aes_cipher_fi.53727189237973939748113923518951983138760529180307102577384264285084761185528
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/18.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 32.aes_cipher_fi.10325259869595730492733239596857250310194369957756441021058560950419433592023
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/32.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 3 more failures.
- Test aes_control_fi has 10 failures.
  - 52.aes_control_fi.65358235973527885567407001473281185209283104016139790667553944042762160512713
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/52.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 101.aes_control_fi.10650834948125870881134990540569780944652999612811807614168478091232955985767
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/101.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 8 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_control_fi has 12 failures.
  - 7.aes_control_fi.89595162914498671936884438648046221727311963305422442571422659835261634382461
    Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011602500 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011602500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 26.aes_control_fi.114864858588213974112601673775487818214505335528457804787636056344462935049214
    Line 143, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005029201 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005029201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 10 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.77085437711765915031614329567206344203286975755463720702119392179411042269979
Line 970, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2309322367 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2309322367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.29382575927594351472909658228896459690619659292261350550633523434799974804422
Line 685, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3381925481 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3381925481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 16.aes_cipher_fi.46755110660997724291765074697726917503991612099836923015385586889333537026606
    Line 136, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007304206 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007304206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 27.aes_cipher_fi.18177495765997766410471934884140997837386221408688841674739281455045743936646
    Line 145, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/27.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005035651 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005035651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.72722403713691300867175972341275329639185976593988338779765934071365273798663
    Line 537, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 772234540 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 772234540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_scoreboard.sv:611) scoreboard [scoreboard] # * has 1 failures:
- Test aes_clear has 1 failures.
  - 2.aes_clear.110589623563996979760926910817679957644564510939033039482875231275701448375984
    Line 2367, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_clear/latest/run.log
```
  UVM_FATAL @  40943389 ps: (aes_scoreboard.sv:611) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
           TEST FAILED MESSAGES DID NOT MATCH

                 0 8f 	 28 	 05 	 0
                 1 00 	 ae 	 a4 	 0
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.73735474978218236686598036406721700916272706445281784455943491237957055761927
    Line 148, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  79552270 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  79552270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.48195325394416989675475040354134344113129696593279755944601265419731357461640
    Line 1173, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4962445868 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 4962445868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 34.aes_core_fi.5244342678240549918264721801101342522097052285941274418426559264717152196122
    Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/34.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010970320 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010970320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 35.aes_core_fi.54794459921004791824098650277690374333066801709705741350125589761207697111397
    Line 145, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/35.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10025913786 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0xd9893384, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
  UVM_INFO @ 10025913786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```