CSRNG Simulation Results

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	239.798us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	30.495us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	248.065us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	29.000s	1.445ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	277.389us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	4.000s	311.150us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	248.065us	20	20	100.00
		csrng_csr_aliasing	6.000s	277.389us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	18.000s	859.126us	198	200	99.00
V2	alerts	csrng_alert	1.133m	5.960ms	500	500	100.00
V2	err	csrng_err	4.000s	21.980us	495	500	99.00
V2	cmds	csrng_cmds	5.050m	24.021ms	50	50	100.00
V2	life cycle	csrng_cmds	5.050m	24.021ms	50	50	100.00
V2	stress_all	csrng_stress_all	25.033m	115.881ms	47	50	94.00
V2	intr_test	csrng_intr_test	3.000s	32.710us	50	50	100.00
V2	alert_test	csrng_alert_test	6.000s	239.578us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	9.000s	422.888us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	9.000s	422.888us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	30.495us	5	5	100.00
		csrng_csr_rw	4.000s	248.065us	20	20	100.00
		csrng_csr_aliasing	6.000s	277.389us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	176.038us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	30.495us	5	5	100.00
		csrng_csr_rw	4.000s	248.065us	20	20	100.00
		csrng_csr_aliasing	6.000s	277.389us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	176.038us	20	20	100.00
V2		TOTAL			1430	1440	99.31
V2S	tl_intg_err	csrng_sec_cm	7.000s	731.638us	5	5	100.00
		csrng_tl_intg_err	34.000s	1.055ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	3.000s	22.567us	50	50	100.00
		csrng_csr_rw	4.000s	248.065us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.133m	5.960ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	25.033m	115.881ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	18.000s	859.126us	198	200	99.00
		csrng_err	4.000s	21.980us	495	500	99.00
		csrng_sec_cm	7.000s	731.638us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	18.000s	859.126us	198	200	99.00
		csrng_err	4.000s	21.980us	495	500	99.00
		csrng_sec_cm	7.000s	731.638us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	18.000s	859.126us	198	200	99.00
		csrng_err	4.000s	21.980us	495	500	99.00
		csrng_sec_cm	7.000s	731.638us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	18.000s	859.126us	198	200	99.00
		csrng_err	4.000s	21.980us	495	500	99.00
		csrng_sec_cm	7.000s	731.638us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	18.000s	859.126us	198	200	99.00
		csrng_err	4.000s	21.980us	495	500	99.00
		csrng_sec_cm	7.000s	731.638us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	18.000s	859.126us	198	200	99.00
		csrng_err	4.000s	21.980us	495	500	99.00
		csrng_sec_cm	7.000s	731.638us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	18.000s	859.126us	198	200	99.00
		csrng_err	4.000s	21.980us	495	500	99.00
		csrng_sec_cm	7.000s	731.638us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.133m	5.960ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	18.000s	859.126us	198	200	99.00
		csrng_err	4.000s	21.980us	495	500	99.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	25.033m	115.881ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.133m	5.960ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	34.000s	1.055ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	18.000s	859.126us	198	200	99.00
		csrng_err	4.000s	21.980us	495	500	99.00
		csrng_sec_cm	7.000s	731.638us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	18.000s	859.126us	198	200	99.00
		csrng_err	4.000s	21.980us	495	500	99.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	18.000s	859.126us	198	200	99.00
		csrng_err	4.000s	21.980us	495	500	99.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	18.000s	859.126us	198	200	99.00
		csrng_err	4.000s	21.980us	495	500	99.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	18.000s	859.126us	198	200	99.00
		csrng_err	4.000s	21.980us	495	500	99.00
		csrng_sec_cm	7.000s	731.638us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	18.000s	859.126us	198	200	99.00
		csrng_err	4.000s	21.980us	495	500	99.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	6.950m	16.724ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1620	1630	99.39

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.64	98.55	96.43	99.94	97.20	92.08	100.00	95.61	90.46

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed has 7 failures:

  • Test csrng_err has 5 failures.

    • 101.csrng_err.97244175757287204028642740267078253994508664233633138639014501260380525123929
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/101.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 2972795 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @   2972795 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   2972795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 209.csrng_err.103886731212075664567227586134805900392928226933711203713473249853526247855084
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/209.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 37571046 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @  37571046 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  37571046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

  • Test csrng_intr has 2 failures.

    • 144.csrng_intr.94015389391768807718250654849746296465348404546652700952944947131211914368226
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/144.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 140164998 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @ 140164998 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @ 140164998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 168.csrng_intr.62383279883526612753615794544394012702955224675955550736853941484194792493281
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/168.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 113227004 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @ 113227004 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @ 113227004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:

  • Test csrng_stress_all has 3 failures.

    • 5.csrng_stress_all.35335575024190452485850994991505135140175295170643841323045919113753677112082
      Line 148, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/5.csrng_stress_all/latest/run.log

        UVM_ERROR @ 12960182126 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 12960182126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 11.csrng_stress_all.1273759623593133753337500509133927339485611181472540171567037627570477879690
      Line 166, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/11.csrng_stress_all/latest/run.log

        UVM_ERROR @ 5059505415 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 5059505415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.