EDN Simulation Results

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.380s	19.328us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.260s	44.386us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.360s	18.180us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.680s	356.197us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.880s	36.548us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.940s	60.759us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.360s	18.180us	20	20	100.00
		edn_csr_aliasing	1.880s	36.548us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	11.150s	1.124ms	300	300	100.00
V2	csrng_commands	edn_genbits	11.150s	1.124ms	300	300	100.00
V2	genbits	edn_genbits	11.150s	1.124ms	300	300	100.00
V2	interrupts	edn_intr	1.600s	21.293us	50	50	100.00
V2	alerts	edn_alert	1.790s	33.969us	200	200	100.00
V2	errs	edn_err	1.680s	30.444us	100	100	100.00
V2	disable	edn_disable	1.310s	14.042us	50	50	100.00
		edn_disable_auto_req_mode	1.730s	46.536us	49	50	98.00
V2	stress_all	edn_stress_all	8.550s	451.057us	50	50	100.00
V2	intr_test	edn_intr_test	1.330s	31.663us	50	50	100.00
V2	alert_test	edn_alert_test	1.810s	59.433us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.860s	126.599us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.860s	126.599us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.260s	44.386us	5	5	100.00
		edn_csr_rw	1.360s	18.180us	20	20	100.00
		edn_csr_aliasing	1.880s	36.548us	5	5	100.00
		edn_same_csr_outstanding	1.640s	22.061us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.260s	44.386us	5	5	100.00
		edn_csr_rw	1.360s	18.180us	20	20	100.00
		edn_csr_aliasing	1.880s	36.548us	5	5	100.00
		edn_same_csr_outstanding	1.640s	22.061us	20	20	100.00
V2		TOTAL			939	940	99.89
V2S	tl_intg_err	edn_sec_cm	10.300s	3.575ms	5	5	100.00
		edn_tl_intg_err	3.570s	274.066us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.340s	28.045us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.790s	33.969us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	10.300s	3.575ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	10.300s	3.575ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	10.300s	3.575ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	10.300s	3.575ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.790s	33.969us	200	200	100.00
		edn_sec_cm	10.300s	3.575ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.790s	33.969us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.570s	274.066us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	2.038m	77.968ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			1109	1130	98.14

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.47	98.87	94.29	97.02	90.70	96.33	97.56	93.51

Failure Buckets

• Job timed out after * minutes has 20 failures:
  • Test edn_stress_all_with_rand_reset has 20 failures.

    • 3.edn_stress_all_with_rand_reset.7857085760181754162972793909129308934389604322712803343250889355135708599615
      Log /nightly/current_run/scratch/master/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • 6.edn_stress_all_with_rand_reset.12361571258675478188883417012837685345948701124182705786093301396880331412031
      Log /nightly/current_run/scratch/master/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • ... and 18 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test edn_disable_auto_req_mode has 1 failures.

    • 22.edn_disable_auto_req_mode.24546888718454605460023135749584258574635631253919591088511118122901740597614
      Line 87, in log /nightly/current_run/scratch/master/edn-sim-vcs/22.edn_disable_auto_req_mode/latest/run.log

        UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---