ENTROPY_SRC/RNG_4BITS Simulation Results

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 3.000s 26.229us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 18.000s 29.883us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 14.000s 139.179us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 16.000s 675.433us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 16.000s 246.396us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 3.000s 537.907us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 14.000s 139.179us 20 20 100.00
entropy_src_csr_aliasing 16.000s 246.396us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 3.000s 26.229us 50 50 100.00
entropy_src_rng 9.267m 19.066ms 300 300 100.00
entropy_src_fw_ov 10.450m 20.036ms 298 300 99.33
V2 firmware_mode entropy_src_fw_ov 10.450m 20.036ms 298 300 99.33
V2 rng_mode entropy_src_rng 9.267m 19.066ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 15.450m 20.014ms 394 400 98.50
V2 health_checks entropy_src_rng 9.267m 19.066ms 300 300 100.00
V2 conditioning entropy_src_rng 9.267m 19.066ms 300 300 100.00
V2 interrupts entropy_src_rng 9.267m 19.066ms 300 300 100.00
entropy_src_intr 47.000s 2.226ms 50 50 100.00
V2 alerts entropy_src_rng 9.267m 19.066ms 300 300 100.00
entropy_src_functional_alerts 7.000s 400.100us 50 50 100.00
V2 stress_all entropy_src_stress_all 1.569h 10.000s 49 50 98.00
V2 functional_errors entropy_src_functional_errors 7.250m 10.013ms 992 1000 99.20
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 14.000s 1.353ms 50 50 100.00
V2 intr_test entropy_src_intr_test 27.000s 36.183us 50 50 100.00
V2 alert_test entropy_src_alert_test 3.000s 34.299us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 33.000s 54.963us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 33.000s 54.963us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 18.000s 29.883us 5 5 100.00
entropy_src_csr_rw 14.000s 139.179us 20 20 100.00
entropy_src_csr_aliasing 16.000s 246.396us 5 5 100.00
entropy_src_same_csr_outstanding 4.000s 144.743us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 18.000s 29.883us 5 5 100.00
entropy_src_csr_rw 14.000s 139.179us 20 20 100.00
entropy_src_csr_aliasing 16.000s 246.396us 5 5 100.00
entropy_src_same_csr_outstanding 4.000s 144.743us 20 20 100.00
V2 TOTAL 2323 2340 99.27
V2S tl_intg_err entropy_src_sec_cm 4.000s 332.848us 5 5 100.00
entropy_src_tl_intg_err 35.000s 124.383us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 9.267m 19.066ms 300 300 100.00
entropy_src_cfg_regwen 3.000s 132.762us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 9.267m 19.066ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 9.267m 19.066ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 9.267m 19.066ms 300 300 100.00
entropy_src_fw_ov 10.450m 20.036ms 298 300 99.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 7.250m 10.013ms 992 1000 99.20
entropy_src_sec_cm 4.000s 332.848us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 7.250m 10.013ms 992 1000 99.20
entropy_src_sec_cm 4.000s 332.848us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 9.267m 19.066ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 7.250m 10.013ms 992 1000 99.20
entropy_src_sec_cm 4.000s 332.848us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 7.250m 10.013ms 992 1000 99.20
entropy_src_sec_cm 4.000s 332.848us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 7.250m 10.013ms 992 1000 99.20
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 7.000s 400.100us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 35.000s 124.383us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 8.467m 20.047ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 2553 2570 99.34

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
94.13 97.38 93.30 98.36 95.16 79.99 96.88 89.27 95.85

Failure Buckets