I2C Simulation Results

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: `7302728`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.373m	1.988ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	34.620s	8.083ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.140s	23.865us	5	5	100.00
V1	csr_rw	i2c_csr_rw	1.050s	28.220us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.320s	985.123us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.060s	215.385us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.500s	66.341us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.050s	28.220us	20	20	100.00
		i2c_csr_aliasing	2.060s	215.385us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	10.400s	1.093ms	0	50	0.00
V2	host_stress_all	i2c_host_stress_all	48.463m	34.254ms	13	50	26.00
V2	host_maxperf	i2c_host_perf	45.326m	48.299ms	49	50	98.00
V2	host_override	i2c_host_override	1.070s	19.863us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.826m	5.222ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.097m	4.818ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.800s	741.334us	50	50	100.00
		i2c_host_fifo_fmt_empty	22.640s	1.943ms	50	50	100.00
		i2c_host_fifo_reset_rx	9.640s	182.751us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.169m	3.139ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	34.980s	3.533ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	5.300s	545.378us	15	50	30.00
V2	target_glitch	i2c_target_glitch	2.620s	938.683us	0	2	0.00
V2	target_stress_all	i2c_target_stress_all	23.031m	58.227ms	47	50	94.00
V2	target_maxperf	i2c_target_perf	8.560s	3.734ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	58.380s	1.608ms	50	50	100.00
		i2c_target_intr_smoke	8.620s	5.624ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.360s	253.584us	50	50	100.00
		i2c_target_fifo_reset_tx	2.700s	319.642us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	30.315m	73.905ms	50	50	100.00
		i2c_target_stress_rd	58.380s	1.608ms	50	50	100.00
		i2c_target_intr_stress_wr	6.498m	24.545ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	9.750s	1.379ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	2.876m	3.769ms	41	50	82.00
V2	bad_address	i2c_target_bad_addr	9.760s	1.831ms	48	50	96.00
V2	target_mode_glitch	i2c_target_hrst	41.820s	10.156ms	24	50	48.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	4.360s	521.218us	50	50	100.00
		i2c_target_fifo_watermarks_tx	2.170s	823.813us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	45.326m	48.299ms	49	50	98.00
		i2c_host_perf_precise	36.849m	24.330ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	34.980s	3.533ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	12.310s	1.196ms	48	50	96.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	4.180s	2.284ms	50	50	100.00
		i2c_target_nack_acqfull_addr	3.930s	2.318ms	50	50	100.00
		i2c_target_nack_txstretch	2.320s	401.992us	34	50	68.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	27.880s	816.883us	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.420s	640.917us	50	50	100.00
V2	alert_test	i2c_alert_test	1.040s	123.173us	50	50	100.00
V2	intr_test	i2c_intr_test	1.010s	22.977us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.610s	138.833us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.610s	138.833us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.140s	23.865us	5	5	100.00
		i2c_csr_rw	1.050s	28.220us	20	20	100.00
		i2c_csr_aliasing	2.060s	215.385us	5	5	100.00
		i2c_same_csr_outstanding	1.510s	137.595us	19	20	95.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.140s	23.865us	5	5	100.00
		i2c_csr_rw	1.050s	28.220us	20	20	100.00
		i2c_csr_aliasing	2.060s	215.385us	5	5	100.00
		i2c_same_csr_outstanding	1.510s	137.595us	19	20	95.00
V2		TOTAL			1608	1792	89.73
V2S	tl_intg_err	i2c_tl_intg_err	2.400s	585.824us	20	20	100.00
		i2c_sec_cm	1.380s	221.370us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.400s	585.824us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	27.570s	2.153ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.900s	1.117ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	17.670s	3.995ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1788	2042	87.56

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
84.02	97.25	89.10	74.17	47.62	93.83	96.41	89.75

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 92 failures:

Test i2c_host_error_intr has 50 failures.

0.i2c_host_error_intr.81648107062343567769671862080577031873511936255256133679835761772873294721462
Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  28765418 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  28765418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_error_intr.464358345806138185775351419602782300185617946588353168457393311136591548324
Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 380394340 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 380394340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 48 more failures.

Test i2c_host_stress_all has 26 failures.

0.i2c_host_stress_all.108811291588260379795195201284572508686341265157801031933881290853030427518819
Line 134, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 27817830786 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 27817830786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all.115370901189457486700458265487386689245916340073367327727090979929893995493567
Line 119, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 4114432686 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 4114432686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 24 more failures.

Test i2c_host_mode_toggle has 14 failures.

2.i2c_host_mode_toggle.4176449802269081786344261758426681110024389722873189620971519311255942772835
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  25875605 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  25875605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.i2c_host_mode_toggle.107181522767582788166371961844776413300524414441256446346150121624722477464561
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/9.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  59648265 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  59648265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

Test i2c_target_stress_all_with_rand_reset has 2 failures.

7.i2c_target_stress_all_with_rand_reset.55760857326577914723782559680899519967642375193542116124976067620418344301499
Line 101, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2870380336 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 2870380336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.i2c_target_stress_all_with_rand_reset.40892185096665432276281747425349126400924732691807859985565004945400221243515
Line 103, in log /nightly/current_run/scratch/master/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3635821730 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 3635821730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 29 failures:
- Test i2c_target_unexp_stop has 29 failures.
  - 0.i2c_target_unexp_stop.30589414331316946497653350385144778795256938530222477233848020884823813069714
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  17050201 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 64 [0x40])
  UVM_INFO @  17050201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_unexp_stop.15632562116129469108241716916149900036029564895000025897934938415534149529454
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 102363785 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 245 [0xf5])
  UVM_INFO @ 102363785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 27 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 26 failures:
- Test i2c_target_hrst has 26 failures.
  - 3.i2c_target_hrst.57827652007990022650739200775705423415657472310608846354474118413363629740658
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10003708360 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10003708360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_hrst.11467995511140146632330934498902633850065194039892724325793023624490957898924
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10178841748 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10178841748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 24 more failures.

UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.78209458265086160565568318707035386340818630650226212218630984904583206106875
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 811452564 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 811452564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.20289748930120944636541602425168034405437088682575503951510436006706056427434
Line 93, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 382633576 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 382633576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 6 failures.

0.i2c_target_stress_all_with_rand_reset.8262516454576289363070852144027110432032389738789235366534699265450048585537
Line 80, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1701617249 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1701617249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_stress_all_with_rand_reset.40498867286204272565291897395956326383431844104811969956207174104770631104844
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1397082338 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1397082338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 16 failures:
- Test i2c_target_nack_txstretch has 16 failures.
  - 3.i2c_target_nack_txstretch.18661040467295528720510775167242427436723279073119659984656750595416244018736
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 401992137 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 401992137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.i2c_target_nack_txstretch.3083349507624363645663864854320135526217793766836771526013838837872591470906
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 730542950 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 730542950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 14 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 15 failures:
- Test i2c_target_unexp_stop has 15 failures.
  - 2.i2c_target_unexp_stop.39711261663548463308342751216289926455695337883283256023411872315651320249236
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 845464777 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 845464777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.i2c_target_unexp_stop.92996240051085273872327045726380521904321297578372850484683850350440048845661
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 292993007 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 292993007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 13 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 14 failures:

Test i2c_host_mode_toggle has 14 failures.

8.i2c_host_mode_toggle.96417371508532036595413358026438077285807027844895040710014663309829534076754
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 268700651 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

16.i2c_host_mode_toggle.30096291531932128068320443841224692019056768264729549665770766306600520245496
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/16.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 166904501 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 12 more failures.

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 11 failures:

Test i2c_host_stress_all has 7 failures.

3.i2c_host_stress_all.69306020942482386000678508248844595693123931214287983696910514194538175602205
Line 154, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 109826680194 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @31419293

22.i2c_host_stress_all.55629642749369066794712930198686043148235695582407287592787275633893630865208
Line 137, in log /nightly/current_run/scratch/master/i2c-sim-vcs/22.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 76151312550 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @20696443

... and 5 more failures.

Test i2c_host_mode_toggle has 4 failures.

10.i2c_host_mode_toggle.36879779064707434675451791374197173749723091405550033830990123516896926125568
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/10.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  83648969 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @44848

12.i2c_host_mode_toggle.61292991990759707830667197941635043192187678222669636825277665402626830089606
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/12.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 112307684 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @10012

... and 2 more failures.

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 9 failures:
- Test i2c_target_stretch has 9 failures.
  - 2.i2c_target_stretch.38236147833464957020384502472076355135623184767209313218342001543728276739185
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10001994291 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10001994291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_stretch.111593253242039756901322133880687910145548874536912720298626632041074434267429
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10004164288 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10004164288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:

Test i2c_target_unexp_stop has 6 failures.

23.i2c_target_unexp_stop.29194736702607404642137939002746580712305413136962797333134781390670256568361
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/23.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 379782025 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 379782025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

32.i2c_target_unexp_stop.59978815595375218571852091302727613115346603640363317992379316387615404411196
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/32.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 160541184 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 160541184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 3 failures:
- Test i2c_target_stress_all has 3 failures.
  - 2.i2c_target_stress_all.77209361873714857239155806039673517551745956163875963196201230389709887373387
    Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 25796478222 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 25796478222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.i2c_target_stress_all.30272843894874326384209392113577389656506149120848799517383551577692945391846
    Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 24392206263 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 24392206263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
- Test i2c_host_mode_toggle has 3 failures.
  - 6.i2c_host_mode_toggle.13188874090716589387795050739129898213829458993829973018029415466519411897037
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 103803817 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x11724894, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 103803817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 14.i2c_host_mode_toggle.36511367756916963149967587229793152190410174176220278043472812862923713086377
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/14.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  65108421 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x5603cd14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  65108421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test i2c_host_stress_all has 1 failures.
  - 15.i2c_host_stress_all.84648769558749563003575674818697010424647101839354975604596775080633615489240
    Line 144, in log /nightly/current_run/scratch/master/i2c-sim-vcs/15.i2c_host_stress_all/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_bad_addr has 2 failures.
  - 15.i2c_target_bad_addr.100826607636878111705898982564134537882206201065429017906563210673587178551827
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/15.i2c_target_bad_addr/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 44.i2c_target_bad_addr.105785552810818892421674902814948340381699683378022129956942852263334778244315
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/44.i2c_target_bad_addr/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:

Test i2c_target_glitch has 2 failures.

0.i2c_target_glitch.35266508736789389362961786651423167145248682169533654117172618835852409005504
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 938683188 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 938683188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_glitch.39955688780931119668273619020391532669312104202514736915045931987640113107199
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 363381965 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 363381965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 3.i2c_target_stress_all_with_rand_reset.91470014594906247820863284854263740700267719220168330776291175651583661447895
    Line 105, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 463603876 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 463603876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.i2c_target_stress_all_with_rand_reset.63250332634569030254041287304286783499251772777243944212677569158377510943705
    Line 94, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 342480330 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 342480330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 2 failures:
- Test i2c_host_perf has 1 failures.
  - 4.i2c_host_perf.112933858020493612286838851637637943277928228473592604498591974883998229957
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_host_perf/latest/run.log
```
  Job timed out after 60 minutes
```
- Test i2c_host_stress_all has 1 failures.
  - 5.i2c_host_stress_all.92230904877585542660306280066794381642105178213295766551380479760011777062990
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 2 failures:

Test i2c_host_stress_all has 2 failures.

17.i2c_host_stress_all.9817124115628489935673404175741582282206685848042101843965298626479267882408
Line 138, in log /nightly/current_run/scratch/master/i2c-sim-vcs/17.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 177663279303 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2793749

28.i2c_host_stress_all.53063030891201918478511566083896727685966130760745703971902886253277279279788
Line 118, in log /nightly/current_run/scratch/master/i2c-sim-vcs/28.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 8489249668 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @7224017

Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
- Test i2c_target_tx_stretch_ctrl has 2 failures.
  - 26.i2c_target_tx_stretch_ctrl.18177896950473360753664982682195697262481932938077084709567413528330426412305
    Line 127, in log /nightly/current_run/scratch/master/i2c-sim-vcs/26.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 40.i2c_target_tx_stretch_ctrl.46780114284574334910869617463522974734092632919791668639642154867126019094933
    Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/40.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_ERROR (cip_base_vseq.sv:840) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test i2c_same_csr_outstanding has 1 failures.
  - 7.i2c_same_csr_outstanding.63597168384628186650273971963939811728785323722070885821154059388890609425423
    Line 74, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @ 147320159 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @ 147320159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```