KEYMGR Simulation Results

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: `7302728`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	25.700s	1.406ms	49	50	98.00
V1	random	keymgr_random	35.310s	8.341ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.790s	252.944us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.760s	28.837us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	18.280s	882.431us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	10.470s	1.705ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.080s	27.583us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.760s	28.837us	20	20	100.00
		keymgr_csr_aliasing	10.470s	1.705ms	5	5	100.00
V1		TOTAL			154	155	99.35
V2	cfgen_during_op	keymgr_cfg_regwen	1.201m	2.066ms	50	50	100.00
V2	sideload	keymgr_sideload	32.860s	4.847ms	50	50	100.00
		keymgr_sideload_kmac	26.830s	1.079ms	50	50	100.00
		keymgr_sideload_aes	31.390s	1.639ms	50	50	100.00
		keymgr_sideload_otbn	44.580s	1.794ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	18.750s	2.720ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	22.020s	4.208ms	48	50	96.00
V2	kmac_error_response	keymgr_kmac_rsp_err	14.900s	2.470ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	48.980s	2.087ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	24.130s	1.246ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	11.110s	8.389ms	50	50	100.00
V2	stress_all	keymgr_stress_all	2.031m	30.181ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.130s	23.188us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.210s	55.809us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.180s	475.607us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.180s	475.607us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.790s	252.944us	5	5	100.00
		keymgr_csr_rw	1.760s	28.837us	20	20	100.00
		keymgr_csr_aliasing	10.470s	1.705ms	5	5	100.00
		keymgr_same_csr_outstanding	3.320s	495.867us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.790s	252.944us	5	5	100.00
		keymgr_csr_rw	1.760s	28.837us	20	20	100.00
		keymgr_csr_aliasing	10.470s	1.705ms	5	5	100.00
		keymgr_same_csr_outstanding	3.320s	495.867us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	sec_cm_additional_check	keymgr_sec_cm	13.480s	1.042ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	13.480s	1.042ms	5	5	100.00
		keymgr_tl_intg_err	6.360s	231.634us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.520s	549.695us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.520s	549.695us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.520s	549.695us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.520s	549.695us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.860s	5.544ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	13.480s	1.042ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	13.480s	1.042ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	6.360s	231.634us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.520s	549.695us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.201m	2.066ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	35.310s	8.341ms	50	50	100.00
		keymgr_csr_rw	1.760s	28.837us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	35.310s	8.341ms	50	50	100.00
		keymgr_csr_rw	1.760s	28.837us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	35.310s	8.341ms	50	50	100.00
		keymgr_csr_rw	1.760s	28.837us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	22.020s	4.208ms	48	50	96.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	24.130s	1.246ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	24.130s	1.246ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	35.310s	8.341ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	13.980s	733.595us	49	50	98.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	13.480s	1.042ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	13.480s	1.042ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	13.480s	1.042ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	20.150s	2.026ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	22.020s	4.208ms	48	50	96.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	13.480s	1.042ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	13.480s	1.042ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	13.480s	1.042ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	20.150s	2.026ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	20.150s	2.026ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	13.480s	1.042ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	20.150s	2.026ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	13.480s	1.042ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	20.150s	2.026ms	50	50	100.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	23.960s	3.759ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1083	1110	97.57

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.38	99.09	98.22	98.90	97.67	98.92	97.71	91.16

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test keymgr_stress_all_with_rand_reset has 21 failures.
  - 2.keymgr_stress_all_with_rand_reset.42384608350170692881330380482494314964911814540584874018829810094964920940661
    Line 995, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 403358617 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 403358617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.keymgr_stress_all_with_rand_reset.32080400108000812099244341365882872372688410516070269126253112771463509985695
    Line 520, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1331441814 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1331441814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 19 more failures.
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
- Test keymgr_smoke has 1 failures.
  - 31.keymgr_smoke.48483315574989448101245273080333111746951045299120232554100813700450178365803
    Line 92, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/31.keymgr_smoke/latest/run.log
```
  UVM_ERROR @   5914056 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   5914056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sideload_protect has 1 failures.
  - 39.keymgr_sideload_protect.20847923396586385092415765320011305014681236788274385371266767932852800236811
    Line 140, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/39.keymgr_sideload_protect/latest/run.log
```
  UVM_ERROR @   7649439 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   7649439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StOwnerIntKey for Attestation Kmac has 1 failures:

Test keymgr_lc_disable has 1 failures.

2.keymgr_lc_disable.98439880427431646193089374726196403081845796570975264040651557544748332832973
Line 371, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/2.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 4208366552 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (2164490354717180271839221814945711286176693349267421067822060570366470723163993588212713071250156373720262195557366132273933484210684654612059632009330116 [0x2953cef7d18e9e944cc67c498e33eefc68ff8fb64dccbc05f86cc1335d6c410d88c014149c6c01a74b5618cbdeaeaef9feb280813757869a7237e25c7a3dbdc4] vs 2164490354717180271839221814945711286176693349267421067822060570366470723163993588212713071250156373720262195557366132273933484210684654612059632009330116 [0x2953cef7d18e9e944cc67c498e33eefc68ff8fb64dccbc05f86cc1335d6c410d88c014149c6c01a74b5618cbdeaeaef9feb280813757869a7237e25c7a3dbdc4]) KMAC key at state StOwnerIntKey for Attestation Kmac
  UVM_INFO @ 4208366552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 29.keymgr_stress_all.5836596895071589219844482733120102717088277423995607782015029570843555035371
    Line 420, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/29.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @  71654350 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3251522938 [0xc1ce4d7a] vs 3251522938 [0xc1ce4d7a]) reg name: keymgr_reg_block.sw_share1_output_3
  UVM_INFO @  71654350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Sealing Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

44.keymgr_stress_all.52615652925950434028917705791684633768481080539542693045708015303862125681852
Line 190, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/44.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 751202349 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (10981730660275932110676939289502243506355425241469614695421675865148211115198043200196698413913825205654744891678730735494780493370860838949129395909897190 [0xd1ad94d1ba0e7b6dcba9fb06dde12af7c34560b90fc4d881bda06611ade665663167f30b47408a043430f0ba86850f558d442bc063b134e8c79698aa75ef2be6] vs 10981730660275932110676939289502243506355425241469614695421675865148211115198043200196698413913825205654744891678730735494780493370860838949129395909897190 [0xd1ad94d1ba0e7b6dcba9fb06dde12af7c34560b90fc4d881bda06611ade665663167f30b47408a043430f0ba86850f558d442bc063b134e8c79698aa75ef2be6]) AES key at state StCreatorRootKey for Sealing Aes
  UVM_INFO @ 751202349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 45.keymgr_lc_disable.32743149512065362417988508505043401957258538737664087714776739351441712183395
    Line 206, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/45.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @ 202327385 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3356127760 [0xc80a7210] vs 3356127760 [0xc80a7210]) reg name: keymgr_reg_block.sw_share0_output_1
  UVM_INFO @ 202327385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```