KMAC/MASKED Simulation Results

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: `7302728`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.621m	17.705ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.670s	20.606us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.620s	54.634us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.720s	5.927ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.970s	3.824ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.570s	71.552us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.620s	54.634us	20	20	100.00
		kmac_csr_aliasing	6.970s	3.824ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.400s	21.399us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.710s	25.078us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	1.108h	140.276ms	50	50	100.00
V2	burst_write	kmac_burst_write	23.421m	160.729ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	38.824m	93.625ms	5	5	100.00
		kmac_test_vectors_sha3_256	25.901m	35.419ms	5	5	100.00
		kmac_test_vectors_sha3_384	27.539m	832.121ms	5	5	100.00
		kmac_test_vectors_sha3_512	21.801m	168.386ms	5	5	100.00
		kmac_test_vectors_shake_128	39.754m	92.590ms	5	5	100.00
		kmac_test_vectors_shake_256	8.003m	106.016ms	5	5	100.00
		kmac_test_vectors_kmac	3.870s	133.010us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.350s	91.547us	5	5	100.00
V2	sideload	kmac_sideload	8.969m	21.555ms	50	50	100.00
V2	app	kmac_app	5.571m	73.786ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.326m	64.626ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.296m	34.387ms	50	50	100.00
V2	error	kmac_error	8.749m	22.421ms	49	50	98.00
V2	key_error	kmac_key_error	19.920s	7.920ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	9.750s	405.405us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	44.270s	6.894ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	26.670s	385.457us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	52.430s	11.875ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	37.280s	1.045ms	50	50	100.00
V2	stress_all	kmac_stress_all	38.126m	524.430ms	49	50	98.00
V2	intr_test	kmac_intr_test	1.330s	16.579us	50	50	100.00
V2	alert_test	kmac_alert_test	1.380s	88.097us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.470s	388.471us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.470s	388.471us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.670s	20.606us	5	5	100.00
		kmac_csr_rw	1.620s	54.634us	20	20	100.00
		kmac_csr_aliasing	6.970s	3.824ms	5	5	100.00
		kmac_same_csr_outstanding	2.150s	90.502us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.670s	20.606us	5	5	100.00
		kmac_csr_rw	1.620s	54.634us	20	20	100.00
		kmac_csr_aliasing	6.970s	3.824ms	5	5	100.00
		kmac_same_csr_outstanding	2.150s	90.502us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.480s	271.132us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.480s	271.132us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.480s	271.132us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.480s	271.132us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.020s	234.857us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.656m	17.443ms	5	5	100.00
		kmac_tl_intg_err	4.090s	265.143us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.090s	265.143us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	37.280s	1.045ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.621m	17.705ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.969m	21.555ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.480s	271.132us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.656m	17.443ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.656m	17.443ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.656m	17.443ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.621m	17.705ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	37.280s	1.045ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.656m	17.443ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.977m	60.087ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.621m	17.705ms	49	50	98.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.663m	6.962ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			935	940	99.47

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.35	99.27	94.49	99.89	80.99	97.15	97.83	97.86

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 0.kmac_stress_all_with_rand_reset.27135099887883972196675123959772726931479509417560111000292409159673001019680
    Line 414, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3791449961 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
  UVM_INFO @ 3791449961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.kmac_stress_all_with_rand_reset.66243340364041760424918567796165970934266693993598106478886275086726906677903
    Line 369, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9052293025 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
  UVM_INFO @ 9052293025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:

Test kmac_smoke has 1 failures.

20.kmac_smoke.83036880221993842825075853066729207778044304907703829883929079696876029099217
Line 74, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/20.kmac_smoke/latest/run.log

  UVM_ERROR @  35460344 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  35460344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

27.kmac_stress_all.89928963475301903890494189324163231709407440024479944175335179957251548117815
Line 77, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/27.kmac_stress_all/latest/run.log

  UVM_ERROR @  99222807 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  99222807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 45.kmac_error.4756439935489200204197524821171677040826961508198412229495566932669802992477
    Line 199, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/45.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```