KMAC/UNMASKED Simulation Results

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	59.670s	12.286ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.450s	32.246us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.510s	61.979us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.680s	4.008ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.320s	3.153ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.020s	437.986us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.510s	61.979us	20	20	100.00
		kmac_csr_aliasing	9.320s	3.153ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.090s	112.848us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.850s	72.395us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	51.194m	553.774ms	50	50	100.00
V2	burst_write	kmac_burst_write	15.252m	189.557ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.860m	258.552ms	5	5	100.00
		kmac_test_vectors_sha3_256	25.834m	234.111ms	5	5	100.00
		kmac_test_vectors_sha3_384	24.286m	133.763ms	5	5	100.00
		kmac_test_vectors_sha3_512	14.896m	47.403ms	5	5	100.00
		kmac_test_vectors_shake_128	3.135m	9.557ms	5	5	100.00
		kmac_test_vectors_shake_256	27.765m	354.768ms	5	5	100.00
		kmac_test_vectors_kmac	3.410s	226.492us	5	5	100.00
		kmac_test_vectors_kmac_xof	2.660s	32.750us	5	5	100.00
V2	sideload	kmac_sideload	8.625m	47.755ms	50	50	100.00
V2	app	kmac_app	5.053m	50.791ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.144m	54.583ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.921m	77.108ms	50	50	100.00
V2	error	kmac_error	6.204m	72.232ms	50	50	100.00
V2	key_error	kmac_key_error	13.080s	6.494ms	49	50	98.00
V2	sideload_invalid	kmac_sideload_invalid	2.153m	10.091ms	41	50	82.00
V2	edn_timeout_error	kmac_edn_timeout_error	50.660s	9.296ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	34.670s	4.347ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.093m	6.948ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	36.640s	1.877ms	50	50	100.00
V2	stress_all	kmac_stress_all	32.621m	124.303ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.150s	14.117us	50	50	100.00
V2	alert_test	kmac_alert_test	1.720s	498.183us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.950s	131.635us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.950s	131.635us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.450s	32.246us	5	5	100.00
		kmac_csr_rw	1.510s	61.979us	20	20	100.00
		kmac_csr_aliasing	9.320s	3.153ms	5	5	100.00
		kmac_same_csr_outstanding	2.960s	359.774us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.450s	32.246us	5	5	100.00
		kmac_csr_rw	1.510s	61.979us	20	20	100.00
		kmac_csr_aliasing	9.320s	3.153ms	5	5	100.00
		kmac_same_csr_outstanding	2.960s	359.774us	20	20	100.00
V2		TOTAL			730	740	98.65
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.660s	92.209us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.660s	92.209us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.660s	92.209us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.660s	92.209us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.390s	674.426us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	47.380s	7.762ms	5	5	100.00
		kmac_tl_intg_err	5.290s	260.422us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.290s	260.422us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	36.640s	1.877ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	59.670s	12.286ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.625m	47.755ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.660s	92.209us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	47.380s	7.762ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	47.380s	7.762ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	47.380s	7.762ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	59.670s	12.286ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	36.640s	1.877ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	47.380s	7.762ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.080m	44.236ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	59.670s	12.286ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.845m	3.580ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			926	940	98.51

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.54	97.59	94.37	100.00	72.73	95.97	97.74	96.40

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 4 failures:

  • Test kmac_sideload_invalid has 4 failures.

    • 6.kmac_sideload_invalid.51897117653034481686417041171094378305078309832115872945362924661885031020702
      Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/6.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10014447239 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1fae6000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 10014447239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 25.kmac_sideload_invalid.98095385561997409618651219090652236459636500072286809192870267591055761344995
      Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/25.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10053991094 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x308a7000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 10053991094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:

  • Test kmac_stress_all_with_rand_reset has 3 failures.

    • 1.kmac_stress_all_with_rand_reset.87015513030041077199805299913969268328740449531013575761731691072985567144720
      Line 149, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2619623677 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2619623677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.kmac_stress_all_with_rand_reset.100421261033101190149027231377370973553244532015898125066538102182138179235158
      Line 348, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27503757328 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 27503757328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:1142) [kmac_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 9.kmac_stress_all_with_rand_reset.93296998762291589375798359607158525602861192892029055720642536362786770030254
      Line 112, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2339960574 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 2339960574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 10.kmac_sideload_invalid.31138284982161128582972444482854974027716120887172634042516875774596806629947
      Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/10.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10208498148 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd0505000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
        UVM_INFO @ 10208498148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:

  • Test kmac_key_error has 1 failures.

    • 12.kmac_key_error.5730248128907334876394876279813720363918844244090746976570995505478122334240
      Line 76, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/12.kmac_key_error/latest/run.log

        UVM_ERROR @ 627709915 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
        UVM_INFO @ 627709915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 21.kmac_sideload_invalid.75653494878207703130356089991471575162195835351864054946374147389315457695736
      Line 86, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/21.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10318480623 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc47a4000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
        UVM_INFO @ 10318480623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 31.kmac_sideload_invalid.24087835768825604693063579519805007560883231189188238019829907933404290736334
      Line 78, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/31.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10020025248 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc4d3c000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
        UVM_INFO @ 10020025248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 35.kmac_sideload_invalid.98016529615117153840571401389369030238306899659148884811824999188800333237499
      Line 92, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/35.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10091269524 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2298b000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
        UVM_INFO @ 10091269524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 46.kmac_sideload_invalid.83214031737323182391067800709539607282879428065096745802790783432604055649486
      Line 80, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/46.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10205403147 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7ab59000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
        UVM_INFO @ 10205403147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---