OTBN Simulation Results

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 12.000s 42.505us 0 1 0.00
V1 single_binary otbn_single 37.000s 251.726us 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 4.000s 15.869us 5 5 100.00
V1 csr_rw otbn_csr_rw 5.000s 19.574us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 13.000s 104.391us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 60.690us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 9.000s 147.586us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 5.000s 19.574us 20 20 100.00
otbn_csr_aliasing 4.000s 60.690us 5 5 100.00
V1 mem_walk otbn_mem_walk 44.000s 7.742ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 16.000s 253.181us 5 5 100.00
V1 TOTAL 65 166 39.16
V2 reset_recovery otbn_reset 1.867m 1.520ms 0 10 0.00
V2 multi_error otbn_multi_err 54.000s 680.350us 0 1 0.00
V2 back_to_back otbn_multi 8.933m 1.930ms 0 10 0.00
V2 stress_all otbn_stress_all 1.350m 252.142us 0 10 0.00
V2 lc_escalation otbn_escalate 1.583m 513.996us 18 60 30.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 10.000s 28.190us 2 5 40.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 27.000s 87.455us 0 10 0.00
V2 alert_test otbn_alert_test 5.000s 32.203us 50 50 100.00
V2 intr_test otbn_intr_test 7.000s 27.140us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 11.000s 63.581us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 11.000s 63.581us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 4.000s 15.869us 5 5 100.00
otbn_csr_rw 5.000s 19.574us 20 20 100.00
otbn_csr_aliasing 4.000s 60.690us 5 5 100.00
otbn_same_csr_outstanding 7.000s 39.755us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 4.000s 15.869us 5 5 100.00
otbn_csr_rw 5.000s 19.574us 20 20 100.00
otbn_csr_aliasing 4.000s 60.690us 5 5 100.00
otbn_same_csr_outstanding 7.000s 39.755us 20 20 100.00
V2 TOTAL 160 246 65.04
V2S mem_integrity otbn_imem_err 12.000s 22.446us 2 10 20.00
otbn_dmem_err 13.000s 34.900us 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 10.000s 103.378us 0 5 0.00
otbn_controller_ispr_rdata_err 20.000s 68.119us 0 5 0.00
otbn_mac_bignum_acc_err 10.000s 55.136us 0 5 0.00
otbn_urnd_err 10.000s 34.389us 0 2 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 7.000s 63.258us 4 5 80.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 7.000s 15.251us 1 2 50.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 8.000s 37.441us 10 10 100.00
V2S tl_intg_err otbn_sec_cm 11.117m 3.286ms 3 5 60.00
otbn_tl_intg_err 35.000s 232.551us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 38.000s 969.506us 19 20 95.00
V2S prim_fsm_check otbn_sec_cm 11.117m 3.286ms 3 5 60.00
V2S prim_count_check otbn_sec_cm 11.117m 3.286ms 3 5 60.00
V2S sec_cm_mem_scramble otbn_smoke 12.000s 42.505us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 13.000s 34.900us 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 12.000s 22.446us 2 10 20.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 35.000s 232.551us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 1.583m 513.996us 18 60 30.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 12.000s 22.446us 2 10 20.00
otbn_dmem_err 13.000s 34.900us 0 15 0.00
otbn_zero_state_err_urnd 10.000s 28.190us 2 5 40.00
otbn_illegal_mem_acc 7.000s 63.258us 4 5 80.00
otbn_sec_cm 11.117m 3.286ms 3 5 60.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 11.117m 3.286ms 3 5 60.00
V2S sec_cm_scramble_key_sideload otbn_single 37.000s 251.726us 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 12.000s 22.446us 2 10 20.00
otbn_dmem_err 13.000s 34.900us 0 15 0.00
otbn_zero_state_err_urnd 10.000s 28.190us 2 5 40.00
otbn_illegal_mem_acc 7.000s 63.258us 4 5 80.00
otbn_sec_cm 11.117m 3.286ms 3 5 60.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 11.117m 3.286ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 1.583m 513.996us 18 60 30.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 12.000s 22.446us 2 10 20.00
otbn_dmem_err 13.000s 34.900us 0 15 0.00
otbn_zero_state_err_urnd 10.000s 28.190us 2 5 40.00
otbn_illegal_mem_acc 7.000s 63.258us 4 5 80.00
otbn_sec_cm 11.117m 3.286ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 11.117m 3.286ms 3 5 60.00
V2S sec_cm_data_reg_sw_sca otbn_single 37.000s 251.726us 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 8.000s 28.039us 0 12 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 13.000s 53.140us 5 5 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 1.150m 187.504us 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 1.150m 187.504us 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 15.000s 2.093ms 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 11.117m 3.286ms 3 5 60.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 11.117m 3.286ms 3 5 60.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 15.000s 86.406us 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 11.117m 3.286ms 3 5 60.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 11.117m 3.286ms 3 5 60.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 15.000s 240.215us 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 15.000s 240.215us 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 9.000s 34.492us 3 7 42.86
V2S sec_cm_data_mem_sec_wipe otbn_single 37.000s 251.726us 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 37.000s 251.726us 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 37.000s 251.726us 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 8.933m 1.930ms 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 37.000s 251.726us 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 37.000s 251.726us 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 20.000s 53.032us 0 5 0.00
V2S sec_cm_key_sideload otbn_single 37.000s 251.726us 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 11.117m 3.286ms 3 5 60.00
V2S TOTAL 67 163 41.10
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 4.717m 1.094ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 292 585 49.91

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
94.20 98.02 74.48 97.24 78.48 60.39 87.18 80.90 98.72

Failure Buckets