7302728| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 35.000s | 174.673us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 2.000s | 13.957us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 2.000s | 11.959us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 3.000s | 380.288us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 2.000s | 112.752us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 2.000s | 128.712us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 2.000s | 11.959us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 2.000s | 112.752us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 54.867m | 600.000ms | 28 | 50 | 56.00 |
| V2 | cnt_rollover | cnt_rollover | 1.617m | 26.292ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 35.000s | 121.944us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.921h | 5.253s | 26 | 50 | 52.00 |
| V2 | alert_test | pattgen_alert_test | 35.000s | 12.639us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 2.000s | 19.721us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 4.000s | 508.430us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 4.000s | 508.430us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 2.000s | 13.957us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 2.000s | 11.959us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 112.752us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 2.000s | 16.264us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 2.000s | 13.957us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 2.000s | 11.959us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 112.752us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 2.000s | 16.264us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 294 | 340 | 86.47 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 3.000s | 255.784us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 35.000s | 83.539us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 3.000s | 255.784us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 2.933m | 12.513ms | 3 | 50 | 6.00 |
| V3 | TOTAL | 3 | 50 | 6.00 | |||
| Unmapped tests | pattgen_inactive_level | 4.183m | 10.021ms | 36 | 50 | 72.00 | |
| TOTAL | 463 | 570 | 81.23 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.53 | 100.00 | 100.00 | 100.00 | 98.50 | 96.61 | -- | 96.95 | 89.42 |
UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 46 failures:
0.pattgen_stress_all_with_rand_reset.93376621318066173407305058725793166804483676861004416164753805286763783237188
Line 133, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 732056112 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 732072158 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 732072158 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 732246070 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.54403496369287053401143695274892897824856714638002053117250707565893093119471
Line 158, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1083841449 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1083859507 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1083859507 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 1083900323 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 44 more failures.
Job timed out after * minutes has 19 failures:
2.pattgen_stress_all.99774783458972212011450420973031190303382990131175947365329517276194220758298
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
18.pattgen_stress_all.55971715954660037063379046500246481860714531050599406242210413810992288710258
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/18.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 7 more failures.
5.pattgen_perf.63828002298637903466066679425468554618666592896082263718851608356276838392122
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/5.pattgen_perf/latest/run.log
Job timed out after 60 minutes
7.pattgen_perf.47789146948752824612120760844854633912290357281880809618374658837751960348610
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/7.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 8 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 14 failures:
0.pattgen_stress_all.10518929463074257719659736426608032995010879403617892552948597272706801829654
Line 133, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
UVM_ERROR @ 279054012771 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10191
1.pattgen_stress_all.38684726543870747762402734253826810988661393767746610080484875260103420719933
Line 127, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all/latest/run.log
UVM_ERROR @ 410424812 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10218
... and 12 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 13 failures:
0.pattgen_perf.102752025946526153549245801194059973247114589222814312386648089330805981182200
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pattgen_perf.22346397314886917105625522966394125335514756243583474449458001968435609910762
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
41.pattgen_stress_all.69204301431169859216017973664705543172801714491360198858356789650462798619267
Line 108, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/41.pattgen_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 2 failures:
8.pattgen_inactive_level.95411512459620253687022917025088722377361709808312539296446737893402766510829
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/8.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10028095002 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xfd45e350, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10028095002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.pattgen_inactive_level.21348207506879807660861647654541782578959402189258750234023433192982679487562
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/14.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10081029757 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x7ab09950, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10081029757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 2 failures:
9.pattgen_inactive_level.95067216092353281451295133141926963536143195412085513873030895193980058286467
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/9.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10132459475 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc1d0f10, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
UVM_INFO @ 10132459475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.pattgen_inactive_level.6951151285735886751160123884071633011212498735915776147429165803446457103217
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/19.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10020666583 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x92e9a310, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
UVM_INFO @ 10020666583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 2 failures:
11.pattgen_inactive_level.93878482377832456272863276750754404665741552318894788307236308596431781525528
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/11.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10199758819 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x1b931bd0, Comparison=CompareOpEq, exp_data=0x0, call_count=14)
UVM_INFO @ 10199758819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.pattgen_inactive_level.52013715013172405342580050732414426470078589915228323383283871593878591599587
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/15.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10016331012 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xad685e10, Comparison=CompareOpEq, exp_data=0x0, call_count=14)
UVM_INFO @ 10016331012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] has 1 failures:
7.pattgen_stress_all_with_rand_reset.12337097718518874240086822820682246174626231563552775733290151087536863446997
Line 129, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/7.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 74866101 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
10.pattgen_inactive_level.56293099994135678284622924208705659870294582676906759984601097348418914574540
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/10.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10015456762 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc60a9910, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10015456762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 1 failures:
22.pattgen_inactive_level.37223794800245009508043357268591226170752136792791072348671141363630153837580
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/22.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10023045033 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x9c9e6c90, Comparison=CompareOpEq, exp_data=0x0, call_count=22)
UVM_INFO @ 10023045033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
27.pattgen_inactive_level.42993948349821295164163391760758708009463472178313984345646795956863580850498
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/27.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10027581099 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa3d72a50, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10027581099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
29.pattgen_inactive_level.73960617831765188613434965349789341222391916750200339958265242600876701736486
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/29.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10720538764 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x627c0750, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
UVM_INFO @ 10720538764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
32.pattgen_inactive_level.51864668768361762125498885444024141170248978841642738100587131597726211298340
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/32.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10040567800 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x98f21390, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10040567800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
35.pattgen_inactive_level.36074231175786545147105610270963759775399050307948274622411910988872649072852
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/35.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10023378609 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe11dc5d0, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
UVM_INFO @ 10023378609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
42.pattgen_inactive_level.101288087245551698130497888478414883476588925377764391732927374487004216295418
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/42.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10123425557 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x23ff31d0, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10123425557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
48.pattgen_inactive_level.75540303913493742536498240753543379786951989028543545263372511880338448488994
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/48.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10023774961 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xc8088410, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10023774961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---