ROM_CTRL/32KB Simulation Results

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: `7302728`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	4.900s	143.781us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.150s	306.533us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.440s	533.066us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.450s	299.403us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.780s	561.932us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.220s	193.138us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.440s	533.066us	20	20	100.00
		rom_ctrl_csr_aliasing	5.780s	561.932us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.640s	170.874us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.370s	184.720us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.150s	232.512us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	26.700s	601.369us	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	12.630s	1.044ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	7.310s	165.914us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	9.940s	290.246us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	9.940s	290.246us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.150s	306.533us	5	5	100.00
		rom_ctrl_csr_rw	7.440s	533.066us	20	20	100.00
		rom_ctrl_csr_aliasing	5.780s	561.932us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.290s	2.086ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.150s	306.533us	5	5	100.00
		rom_ctrl_csr_rw	7.440s	533.066us	20	20	100.00
		rom_ctrl_csr_aliasing	5.780s	561.932us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.290s	2.086ms	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.158m	16.017ms	18	20	90.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	29.960s	861.310us	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.215m	1.425ms	2	5	40.00
		rom_ctrl_tl_intg_err	55.550s	309.391us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.215m	1.425ms	2	5	40.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.215m	1.425ms	2	5	40.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.158m	16.017ms	18	20	90.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.158m	16.017ms	18	20	90.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.158m	16.017ms	18	20	90.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.158m	16.017ms	18	20	90.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.158m	16.017ms	18	20	90.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.215m	1.425ms	2	5	40.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.215m	1.425ms	2	5	40.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	4.900s	143.781us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	4.900s	143.781us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	4.900s	143.781us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	55.550s	309.391us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.158m	16.017ms	18	20	90.00
		rom_ctrl_kmac_err_chk	12.630s	1.044ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.158m	16.017ms	18	20	90.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.158m	16.017ms	18	20	90.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.158m	16.017ms	18	20	90.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	29.960s	861.310us	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.215m	1.425ms	2	5	40.00
V2S		TOTAL			60	65	92.31
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	6.725m	4.505ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			261	266	98.12

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.14	99.59	98.66	100.00	100.00	99.64	96.80	99.28

Failure Buckets

UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 2 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.
  - 0.rom_ctrl_corrupt_sig_fatal_chk.37204835002700085202679970173981820579069126956177847145460613661489381713321
    Line 85, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 939089094 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 939089094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 14.rom_ctrl_corrupt_sig_fatal_chk.75220658027810526898944167159566564505029269811923400110461935841717867021162
    Line 93, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 4584119545 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 4584119545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 2 failures:

Test rom_ctrl_sec_cm has 2 failures.

2.rom_ctrl_sec_cm.86338647062488749656339749056126429136277407645541647770825774249077263199944
Line 291, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 114621768ps failed at 114621768ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 114621768ps failed at 114621768ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

4.rom_ctrl_sec_cm.41680025857650338771349822981273058676843311322252681261796683699742215913663
Line 302, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 63873890ps failed at 63873890ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 63873890ps failed at 63873890ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

Test rom_ctrl_sec_cm has 1 failures.

0.rom_ctrl_sec_cm.24737413307243506228180726715759485610827658807335275120055218303617683737604
Line 180, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  Starting assertion attempts at time 161819193ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
  Starting assertion attempts at time 161819193ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
  Starting assertion attempts at time 161819193ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))