ROM_CTRL/64KB Simulation Results

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	8.610s	563.928us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	11.860s	1.004ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.270s	2.045ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	11.880s	305.866us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.810s	1.069ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	11.860s	296.365us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.270s	2.045ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.810s	1.069ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	10.050s	295.101us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	12.060s	296.847us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	11.750s	539.410us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	54.190s	2.074ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	12.830s	384.801us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	15.430s	1.061ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.690s	1.935ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.690s	1.935ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	11.860s	1.004ms	5	5	100.00
		rom_ctrl_csr_rw	14.270s	2.045ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.810s	1.069ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.810s	519.531us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	11.860s	1.004ms	5	5	100.00
		rom_ctrl_csr_rw	14.270s	2.045ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.810s	1.069ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.810s	519.531us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.043m	44.909ms	20	20	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	59.420s	1.593ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	9.416m	590.825us	1	5	20.00
		rom_ctrl_tl_intg_err	2.262m	968.026us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	9.416m	590.825us	1	5	20.00
V2S	prim_count_check	rom_ctrl_sec_cm	9.416m	590.825us	1	5	20.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.043m	44.909ms	20	20	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.043m	44.909ms	20	20	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.043m	44.909ms	20	20	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.043m	44.909ms	20	20	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.043m	44.909ms	20	20	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	9.416m	590.825us	1	5	20.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	9.416m	590.825us	1	5	20.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	8.610s	563.928us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	8.610s	563.928us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	8.610s	563.928us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.262m	968.026us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.043m	44.909ms	20	20	100.00
		rom_ctrl_kmac_err_chk	12.830s	384.801us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.043m	44.909ms	20	20	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.043m	44.909ms	20	20	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.043m	44.909ms	20	20	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	59.420s	1.593ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	9.416m	590.825us	1	5	20.00
V2S		TOTAL			61	65	93.85
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	4.731m	8.621ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			262	266	98.50

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.14	99.59	98.66	100.00	100.00	99.64	96.80	99.28

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 2 failures:

  • Test rom_ctrl_sec_cm has 2 failures.

    • 0.rom_ctrl_sec_cm.46316247222977980146665991067529896841492315190324531392632704265999127510345
      Line 237, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 45986577ps failed at 45986577ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 45986577ps failed at 45986577ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • 2.rom_ctrl_sec_cm.691481109520440057366286622217644073644247980689501502754013450139411138359
      Line 125, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 6509368ps failed at 6509368ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 6509368ps failed at 6509368ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 2 failures:

  • Test rom_ctrl_sec_cm has 2 failures.

    • 1.rom_ctrl_sec_cm.54156463039829604958777924565302700798630305972871741049942550591151698143340
      Line 182, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 22056006ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 22056006ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 22056006ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
      

    • 3.rom_ctrl_sec_cm.35296827678004535498479431454559620556161617517582006019884333361820004568349
      Line 106, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 5339643ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 5339643ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 5339643ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))