RV_TIMER Simulation Results

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: `7302728`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.730s	593.879us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.840s	106.177us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.760s	15.862us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.070s	583.408us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.180s	38.753us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.720s	36.408us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.760s	15.862us	20	20	100.00
		rv_timer_csr_aliasing	1.180s	38.753us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	3.770s	48.049ms	2	20	10.00
V2	disabled	rv_timer_disabled	3.560s	1.444ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	19.430m	5.613s	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	19.430m	5.613s	10	10	100.00
V2	stress	rv_timer_stress_all	5.760s	4.356ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.920s	30.335us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.790s	17.295us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.590s	138.847us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.590s	138.847us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.840s	106.177us	5	5	100.00
		rv_timer_csr_rw	0.760s	15.862us	20	20	100.00
		rv_timer_csr_aliasing	1.180s	38.753us	5	5	100.00
		rv_timer_same_csr_outstanding	0.900s	39.299us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.840s	106.177us	5	5	100.00
		rv_timer_csr_rw	0.760s	15.862us	20	20	100.00
		rv_timer_csr_aliasing	1.180s	38.753us	5	5	100.00
		rv_timer_same_csr_outstanding	0.900s	39.299us	20	20	100.00
V2		TOTAL			192	210	91.43
V2S	tl_intg_err	rv_timer_sec_cm	1.250s	259.021us	5	5	100.00
		rv_timer_tl_intg_err	1.620s	195.258us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.620s	195.258us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	2.120s	1.286ms	3	10	30.00
V3	max_value	rv_timer_max	1.850s	836.523us	0	10	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	56.830s	6.530ms	17	20	85.00
V3		TOTAL			20	40	50.00
		TOTAL			312	350	89.14

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.77	100.00	100.00	78.66	--	100.00	96.82	99.12

Failure Buckets

UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 25 failures:
- Test rv_timer_min has 7 failures.
  - 0.rv_timer_min.96067002214836073690218276363710681836062375521308341776120879806476362628102
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
```
  UVM_FATAL @  68536872 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x1fd45f04) == 0x1
  UVM_INFO @  68536872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.rv_timer_min.36914896091358161200636445776185293450038533698369953057410454911330477346781
    Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/4.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 201768644 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x290b6f04) == 0x1
  UVM_INFO @ 201768644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
- Test rv_timer_random_reset has 18 failures.
  - 0.rv_timer_random_reset.91767926791850253219846001339773146627900452146187154889668367408103025099322
    Line 74, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 287330147 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x8c1cb504) == 0x1
  UVM_INFO @ 287330147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_random_reset.5128859941384855903317981906564258001715290962284473144556180391233945112759
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1067136146 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc0b7b704) == 0x1
  UVM_INFO @ 1067136146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 9 failures:
- Test rv_timer_max has 9 failures.
  - 1.rv_timer_max.88462786464566688873042973026555899871479662884745837906117878152434943763617
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
```
  UVM_ERROR @ 178999373 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 178999373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.rv_timer_max.30360467052301861705762656030443057956605896405455680894668489708726222189057
    Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/2.rv_timer_max/latest/run.log
```
  UVM_ERROR @  46042406 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  46042406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test rv_timer_stress_all_with_rand_reset has 2 failures.

1.rv_timer_stress_all_with_rand_reset.3251659639194111846882240238142890067034019868583641483259611340893508393920
Line 115, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1216518001 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1216518001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.rv_timer_stress_all_with_rand_reset.34342885486344628721883812687879571828993197042248379284757476292242164012620
Line 233, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/13.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 19697733546 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 19697733546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_timer_scoreboard.sv:365) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) has 1 failures:
- Test rv_timer_max has 1 failures.
  - 0.rv_timer_max.77230649989134863886030358253065825499111613965437078707275711716999160743756
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
```
  UVM_ERROR @  89214879 ps: (rv_timer_scoreboard.sv:365) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
  UVM_INFO @  89214879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 1 failures:
- Test rv_timer_stress_all_with_rand_reset has 1 failures.
  - 19.rv_timer_stress_all_with_rand_reset.18439398328649321486251894137992248735553795169626451227880759982685127066626
    Line 76, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/19.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  58678032 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @  58678032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```