SPI_DEVICE/1R1W Simulation Results

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: `7302728`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	6.670m	258.443ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.820s	47.101us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.990s	100.801us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	29.940s	3.826ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	19.300s	6.541ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.300s	212.573us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.990s	100.801us	20	20	100.00
		spi_device_csr_aliasing	19.300s	6.541ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.060s	13.325us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.310s	117.458us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.200s	21.491us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.120s	2.870us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.720s	3.040us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	6.040s	420.099us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.040s	420.099us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	26.180s	31.787ms	50	50	100.00
		spi_device_tpm_sts_read	1.530s	395.444us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	33.370s	7.198ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	44.280s	14.789ms	50	50	100.00
		spi_device_flash_all	6.451m	245.683ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	32.670s	44.727ms	50	50	100.00
		spi_device_flash_all	6.451m	245.683ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	32.670s	44.727ms	50	50	100.00
		spi_device_flash_all	6.451m	245.683ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.451m	245.683ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	41.610s	4.823ms	50	50	100.00
		spi_device_flash_all	6.451m	245.683ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	41.610s	4.823ms	50	50	100.00
		spi_device_flash_all	6.451m	245.683ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	41.610s	4.823ms	50	50	100.00
		spi_device_flash_all	6.451m	245.683ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	41.610s	4.823ms	50	50	100.00
		spi_device_flash_all	6.451m	245.683ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	41.610s	4.823ms	50	50	100.00
		spi_device_flash_all	6.451m	245.683ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	36.370s	51.677ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.923m	56.261ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.923m	56.261ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.923m	56.261ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	59.540s	4.874ms	50	50	100.00
		spi_device_read_buffer_direct	19.080s	22.422ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.923m	56.261ms	50	50	100.00
		spi_device_flash_all	6.451m	245.683ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.451m	245.683ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.451m	245.683ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	19.560s	11.122ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	19.560s	11.122ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	6.670m	258.443ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	5.954m	53.126ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.493m	625.763ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.130s	18.471us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.140s	54.993us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.970s	336.949us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.970s	336.949us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.820s	47.101us	5	5	100.00
		spi_device_csr_rw	2.990s	100.801us	20	20	100.00
		spi_device_csr_aliasing	19.300s	6.541ms	5	5	100.00
		spi_device_same_csr_outstanding	4.570s	202.707us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.820s	47.101us	5	5	100.00
		spi_device_csr_rw	2.990s	100.801us	20	20	100.00
		spi_device_csr_aliasing	19.300s	6.541ms	5	5	100.00
		spi_device_same_csr_outstanding	4.570s	202.707us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	1.750s	117.694us	5	5	100.00
		spi_device_tl_intg_err	18.010s	4.440ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	18.010s	4.440ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.248m	297.201ms	50	50	100.00
		TOTAL			1130	1151	98.18

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.62	99.11	96.57	71.19	89.36	98.40	94.43	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.15943319307796122045986162146743306001865447079131839520295401438713208996310
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1090187 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[79])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1090187 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1090187 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[975])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.39449618485510425006705690071859625399983105152270162253724662206324688189069
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    906269 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[9])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    906269 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    906269 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[905])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])

has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.17531458172364657780206645193575208627726848286742795314935597011596173672187
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @    919478 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1cce3 [11100110011100011] vs 0x0 [0])
  UVM_ERROR @    924478 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x68e105 [11010001110000100000101] vs 0x0 [0])
  UVM_ERROR @   1011478 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x97b34a [100101111011001101001010] vs 0x0 [0])
  UVM_ERROR @   1021478 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7dc7c7 [11111011100011111000111] vs 0x0 [0])
  UVM_ERROR @   1023478 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc7a0ec [110001111010000011101100] vs 0x0 [0])