SPI_DEVICE/2P Simulation Results

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	7.102m	59.877ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.330s	743.044us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.720s	110.062us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	24.100s	3.735ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.100s	4.693ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.560s	59.896us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.720s	110.062us	20	20	100.00
		spi_device_csr_aliasing	17.100s	4.693ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.840s	10.137us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.300s	274.064us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.210s	140.833us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.440s	28.124us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.130s	49.862us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	4.370s	312.916us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	4.370s	312.916us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.460s	18.717ms	50	50	100.00
		spi_device_tpm_sts_read	1.480s	668.817us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	33.620s	9.875ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	28.130s	23.960ms	50	50	100.00
		spi_device_flash_all	6.883m	89.545ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	27.180s	8.243ms	50	50	100.00
		spi_device_flash_all	6.883m	89.545ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	27.180s	8.243ms	50	50	100.00
		spi_device_flash_all	6.883m	89.545ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.883m	89.545ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	24.450s	6.780ms	50	50	100.00
		spi_device_flash_all	6.883m	89.545ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	24.450s	6.780ms	50	50	100.00
		spi_device_flash_all	6.883m	89.545ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	24.450s	6.780ms	50	50	100.00
		spi_device_flash_all	6.883m	89.545ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	24.450s	6.780ms	50	50	100.00
		spi_device_flash_all	6.883m	89.545ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	24.450s	6.780ms	50	50	100.00
		spi_device_flash_all	6.883m	89.545ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	33.340s	13.326ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.077m	58.906ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.077m	58.906ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.077m	58.906ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	44.330s	4.041ms	50	50	100.00
		spi_device_read_buffer_direct	18.890s	1.693ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.077m	58.906ms	50	50	100.00
		spi_device_flash_all	6.883m	89.545ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.883m	89.545ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.883m	89.545ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	16.000s	1.396ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	16.000s	1.396ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	7.102m	59.877ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	7.740m	428.369ms	50	50	100.00
V2	stress_all	spi_device_stress_all	23.117m	274.072ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.150s	29.307us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.110s	14.837us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.730s	336.312us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.730s	336.312us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.330s	743.044us	5	5	100.00
		spi_device_csr_rw	2.720s	110.062us	20	20	100.00
		spi_device_csr_aliasing	17.100s	4.693ms	5	5	100.00
		spi_device_same_csr_outstanding	4.110s	114.959us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.330s	743.044us	5	5	100.00
		spi_device_csr_rw	2.720s	110.062us	20	20	100.00
		spi_device_csr_aliasing	17.100s	4.693ms	5	5	100.00
		spi_device_same_csr_outstanding	4.110s	114.959us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.790s	779.214us	5	5	100.00
		spi_device_tl_intg_err	16.970s	835.004us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.970s	835.004us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	30.032m	1.500s	49	50	98.00
		TOTAL			1150	1151	99.91

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.16	99.17	96.65	74.78	89.36	98.49	94.41	99.26

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 43.spi_device_flash_mode_ignore_cmds.66712539427648365276600763960750580968672649177571142469174793800764446323726
      Line 135, in log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---