SPI_HOST Simulation Results

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: `7302728`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	2.417m	14.408ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	20.645us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	20.100us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	750.659us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	37.629us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	81.447us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	20.100us	20	20	100.00
		spi_host_csr_aliasing	2.000s	37.629us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	17.915us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	21.702us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	3.000s	191.675us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	1.333m	8.656ms	50	50	100.00
		spi_host_error_cmd	2.000s	47.062us	50	50	100.00
		spi_host_event	10.600m	103.599ms	50	50	100.00
V2	clock_rate	spi_host_speed	7.000s	202.964us	50	50	100.00
V2	speed	spi_host_speed	7.000s	202.964us	50	50	100.00
V2	chip_select_timing	spi_host_speed	7.000s	202.964us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	43.000s	1.763ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	28.654us	50	50	100.00
V2	cpol_cpha	spi_host_speed	7.000s	202.964us	50	50	100.00
V2	full_cycle	spi_host_speed	7.000s	202.964us	50	50	100.00
V2	duplex	spi_host_smoke	2.417m	14.408ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	2.417m	14.408ms	50	50	100.00
V2	stress_all	spi_host_stress_all	2.533m	9.952ms	50	50	100.00
V2	spien	spi_host_spien	4.050m	6.631ms	50	50	100.00
V2	stall	spi_host_status_stall	37.283m	1.000s	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	32.000s	3.964ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	1.333m	8.656ms	50	50	100.00
V2	alert_test	spi_host_alert_test	2.000s	45.359us	50	50	100.00
V2	intr_test	spi_host_intr_test	2.000s	15.733us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	3.000s	358.598us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	3.000s	358.598us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	20.645us	5	5	100.00
		spi_host_csr_rw	2.000s	20.100us	20	20	100.00
		spi_host_csr_aliasing	2.000s	37.629us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	28.535us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	20.645us	5	5	100.00
		spi_host_csr_rw	2.000s	20.100us	20	20	100.00
		spi_host_csr_aliasing	2.000s	37.629us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	28.535us	20	20	100.00
V2		TOTAL			687	690	99.57
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	542.061us	20	20	100.00
		spi_host_sec_cm	2.000s	51.433us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	542.061us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	9.433m	27.727ms	10	10	100.00
		TOTAL			837	840	99.64

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.10	96.82	93.35	98.69	94.35	73.07	100.00	95.21	90.42

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test spi_host_status_stall has 2 failures.
  - 28.spi_host_status_stall.32056658414380358976654854395087717891542825557150166069198075755683521766577
    Line 1557, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/28.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 41.spi_host_status_stall.55888521809638371474484146441897655350562470285315175802607298270004656061102
    Line 7091, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/41.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

Test spi_host_status_stall has 1 failures.

40.spi_host_status_stall.74859364002501461980644946061964158907267953303963735553833135402444337289020
Line 833, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/40.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 99542132 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @  99542132 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time= 99542000 ps
  UVM_INFO @  99542132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---