SRAM_CTRL/MAIN Simulation Results

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.514m	3.221ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.030s	127.567us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.050s	28.060us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.190s	430.524us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.090s	58.202us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.250s	1.304ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.050s	28.060us	20	20	100.00
		sram_ctrl_csr_aliasing	1.090s	58.202us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.842m	153.677ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.986m	21.902ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	25.212m	323.956ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.035m	72.869ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	41.018m	165.573ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	18.820m	15.706ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.888m	228.132ms	50	50	100.00
V2	executable	sram_ctrl_executable	25.095m	26.350ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.709m	1.603ms	50	50	100.00
		sram_ctrl_partial_access_b2b	12.555m	33.405ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.707m	3.053ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.657m	1.292ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.646m	4.172ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	18.764m	59.092ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.450s	3.343ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.715h	80.336ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.060s	89.562us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.800s	2.286ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.800s	2.286ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.030s	127.567us	5	5	100.00
		sram_ctrl_csr_rw	1.050s	28.060us	20	20	100.00
		sram_ctrl_csr_aliasing	1.090s	58.202us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.240s	48.387us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.030s	127.567us	5	5	100.00
		sram_ctrl_csr_rw	1.050s	28.060us	20	20	100.00
		sram_ctrl_csr_aliasing	1.090s	58.202us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.240s	48.387us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.005m	7.349ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.170s	3.730us	0	5	0.00
		sram_ctrl_tl_intg_err	3.250s	401.923us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.170s	3.730us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.250s	401.923us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	18.764m	59.092ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	18.764m	59.092ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.050s	28.060us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	25.095m	26.350ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	25.095m	26.350ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	25.095m	26.350ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.888m	228.132ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	14.940s	13.357ms	42	50	84.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.005m	7.349ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	8.770s	3.876ms	42	50	84.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.514m	3.221ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.514m	3.221ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	25.095m	26.350ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.170s	3.730us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.888m	228.132ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.170s	3.730us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.170s	3.730us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.514m	3.221ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.170s	3.730us	0	5	0.00
V2S		TOTAL			124	145	85.52
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.603m	14.458ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1169	1190	98.24

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.66	99.11	92.90	85.46	100.00	98.02	95.83	98.33

Failure Buckets

• Offending 'reqfifo_rvalid' has 8 failures:
  • Test sram_ctrl_mubi_enc_err has 8 failures.

    • 0.sram_ctrl_mubi_enc_err.86008011920943004430148695628705595341863712205967193551412301541617850799047
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 1344306243 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 1344306243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.sram_ctrl_mubi_enc_err.76327635179677255771671733449976383987973235009307853760500025828563893422814
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 671566427 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 671566427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 6 more failures.

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 8 failures:
  • Test sram_ctrl_readback_err has 8 failures.

    • 3.sram_ctrl_readback_err.89202091486539601827613055790034116420852276996147907354151375250343536825123
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2648286041 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5a) != exp (0x38)
        UVM_INFO @ 2648286041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 11.sram_ctrl_readback_err.51114784616480862708791792357414050683262542068869759930270819168976387556843
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/11.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 691581490 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x47) != exp (0x60)
        UVM_INFO @ 691581490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 6 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:
  • Test sram_ctrl_sec_cm has 4 failures.

    • 0.sram_ctrl_sec_cm.82095645909286184140402433177268202371470100169610994719896152148014285779075
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3730064 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3730064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.35171246963453717084855858687449717757100969932225963414845151125327034695075
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   2435671 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   2435671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 2.sram_ctrl_sec_cm.104445638131257016604017642191668028150189703603872349033470429436380677739586
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   1805677 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   1805677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---