SRAM_CTRL/RET Simulation Results

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: `7302728`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.743m	2.955ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.090s	43.655us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.110s	178.664us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.740s	177.339us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.120s	21.158us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	9.730s	10.003ms	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.110s	178.664us	20	20	100.00
		sram_ctrl_csr_aliasing	1.120s	21.158us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.940s	7.302ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.790s	174.461us	50	50	100.00
V1		TOTAL			202	205	98.54
V2	multiple_keys	sram_ctrl_multiple_keys	25.053m	396.716ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.687m	8.650ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.433m	39.414ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.093m	5.723ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.610s	2.838ms	50	50	100.00
V2	executable	sram_ctrl_executable	24.234m	18.461ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.676m	416.266us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.192m	169.412ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.678m	256.643us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.510m	154.906us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.780m	548.586us	50	50	100.00
V2	regwen	sram_ctrl_regwen	20.373m	305.908ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.200s	29.722us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	51.389m	31.840ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.050s	31.562us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.270s	537.994us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.270s	537.994us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.090s	43.655us	5	5	100.00
		sram_ctrl_csr_rw	1.110s	178.664us	20	20	100.00
		sram_ctrl_csr_aliasing	1.120s	21.158us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.170s	16.580us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.090s	43.655us	5	5	100.00
		sram_ctrl_csr_rw	1.110s	178.664us	20	20	100.00
		sram_ctrl_csr_aliasing	1.120s	21.158us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.170s	16.580us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.170s	1.787ms	19	20	95.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.260s	35.573us	0	5	0.00
		sram_ctrl_tl_intg_err	3.490s	2.940ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.260s	35.573us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.490s	2.940ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	20.373m	305.908ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	20.373m	305.908ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.110s	178.664us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	24.234m	18.461ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	24.234m	18.461ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	24.234m	18.461ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.610s	2.838ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.580s	138.119us	45	50	90.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.170s	1.787ms	19	20	95.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.620s	40.282us	32	50	64.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.743m	2.955ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.743m	2.955ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	24.234m	18.461ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.260s	35.573us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.610s	2.838ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.260s	35.573us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.260s	35.573us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.743m	2.955ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.260s	35.573us	0	5	0.00
V2S		TOTAL			116	145	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	11.287m	13.135ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1158	1190	97.31

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.64	99.07	92.90	85.37	100.00	97.98	95.79	98.33

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 18 failures:
- Test sram_ctrl_readback_err has 18 failures.
  - 0.sram_ctrl_readback_err.58389715867077832086969616292052303963706360217258484734614946167906790203780
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  52127732 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x8) != exp (0x1e)
  UVM_INFO @  52127732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.sram_ctrl_readback_err.39467904514399028167655537465897339974835044842475639054869135581033831887488
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  24976969 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4e) != exp (0x19)
  UVM_INFO @  24976969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.
Offending 'reqfifo_rvalid' has 5 failures:
- Test sram_ctrl_mubi_enc_err has 5 failures.
  - 15.sram_ctrl_mubi_enc_err.112881236968710331824988851733780670971508129464892680030380591523419728205942
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  27429894 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  27429894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 20.sram_ctrl_mubi_enc_err.93840687056043151389441420486417712280386047343530417369547175062313934833545
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  33929369 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  33929369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
Offending '(!$isunknown(rdata_o))' has 2 failures:
- Test sram_ctrl_sec_cm has 2 failures.
  - 0.sram_ctrl_sec_cm.79232886043940849400815068811507086799115049244373080647558996719611665422292
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   2453573 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   2453573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.sram_ctrl_sec_cm.82741761046230165634579942093955914389228105512010395024600482411348361120817
    Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @  14891866 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  14891866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

Test sram_ctrl_sec_cm has 1 failures.

2.sram_ctrl_sec_cm.44900108351455127649286873289199207356060303366328079892256144119976072713062
Line 103, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 33586100ps failed at 33586100ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 33613127ps failed at 33613127ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

Offending '(depth_o <= *'(Depth))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 3.sram_ctrl_sec_cm.93958048376987014847647692476657409368413819832009776843831635724969053218133
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(depth_o <= 2'(Depth))'
  UVM_ERROR @   2695807 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
  UVM_INFO @   2695807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 4.sram_ctrl_sec_cm.1569767702547873763544050575711322394405109596131629210907173279488026903010
    Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @   3981277 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   3981277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '((pend_req[*].pend == *'b0) || $test$plusargs("disable_assert_final_checks"))' has 1 failures:
- Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 5.sram_ctrl_passthru_mem_tl_intg_err.10867696328951190433898219449000672413549060228053982175773757034410938423064
    Line 160, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
      Offending '((pend_req[47].pend == 1'b0) || $test$plusargs("disable_assert_final_checks"))'
  UVM_ERROR @ 875534100 ps: (tlul_assert.sv:319) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
  UVM_INFO @ 875534100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 8.sram_ctrl_csr_mem_rw_with_rand_reset.61899904528462081637929420312617771012292744387102923564872006101551017051121
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 117141958 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (2 [0x2] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @ 117141958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 11.sram_ctrl_csr_mem_rw_with_rand_reset.20168039169350398944211832915610186398092005314151268809136464788302272887716
    Line 93, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10002726821 ps: (sram_ctrl_base_vseq.sv:168) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
  UVM_INFO @ 10002726821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 13.sram_ctrl_csr_mem_rw_with_rand_reset.80095201179073989724693988296225898132844110614798566366709780591265503079047
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  27555798 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (5 [0x5] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  27555798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```