7302728| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 8.680s | 2.107ms | 50 | 50 | 100.00 |
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 10.660s | 2.463ms | 50 | 50 | 100.00 |
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 6.260s | 2.194ms | 5 | 5 | 100.00 |
| V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 6.260s | 2.513ms | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 13.880s | 6.019ms | 5 | 5 | 100.00 |
| V1 | csr_rw | sysrst_ctrl_csr_rw | 8.740s | 2.051ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 1.256m | 43.572ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 10.960s | 2.568ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 8.850s | 2.082ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 8.740s | 2.051ms | 20 | 20 | 100.00 |
| sysrst_ctrl_csr_aliasing | 10.960s | 2.568ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 165 | 165 | 100.00 | |||
| V2 | combo_detect | sysrst_ctrl_combo_detect | 6.780m | 203.774ms | 50 | 50 | 100.00 |
| V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 7.695m | 142.866ms | 94 | 100 | 94.00 |
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 7.109m | 176.476ms | 50 | 50 | 100.00 |
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 11.530s | 3.989ms | 49 | 50 | 98.00 |
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 9.920s | 2.510ms | 50 | 50 | 100.00 |
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 8.330s | 2.201ms | 50 | 50 | 100.00 |
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 18.440s | 4.950ms | 50 | 50 | 100.00 |
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 8.080s | 2.612ms | 50 | 50 | 100.00 |
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 12.069m | 2.293s | 43 | 50 | 86.00 |
| V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 1.042m | 36.102ms | 2 | 2 | 100.00 |
| V2 | stress_all | sysrst_ctrl_stress_all | 9.487m | 541.330ms | 49 | 50 | 98.00 |
| V2 | alert_test | sysrst_ctrl_alert_test | 8.290s | 2.014ms | 50 | 50 | 100.00 |
| V2 | intr_test | sysrst_ctrl_intr_test | 8.540s | 2.010ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 9.930s | 2.077ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 9.930s | 2.077ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 13.880s | 6.019ms | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 8.740s | 2.051ms | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 10.960s | 2.568ms | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 33.470s | 9.097ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 13.880s | 6.019ms | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 8.740s | 2.051ms | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 10.960s | 2.568ms | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 33.470s | 9.097ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 677 | 692 | 97.83 | |||
| V2S | tl_intg_err | sysrst_ctrl_sec_cm | 1.747m | 42.011ms | 5 | 5 | 100.00 |
| sysrst_ctrl_tl_intg_err | 1.794m | 42.487ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 1.794m | 42.487ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 22.390s | 6.158ms | 48 | 50 | 96.00 |
| V3 | TOTAL | 48 | 50 | 96.00 | |||
| TOTAL | 915 | 932 | 98.18 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.47 | 99.42 | 97.65 | 100.00 | 95.51 | 99.48 | 98.28 | 91.92 |
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 5 failures:
Test sysrst_ctrl_ultra_low_pwr has 3 failures.
21.sysrst_ctrl_ultra_low_pwr.77309114475324332862031604023914305454334756661711718773770431258657174404465
Line 382, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 3468740115 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 3468823448 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 3468823448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.sysrst_ctrl_ultra_low_pwr.78294425752818858469208373411909394702815136652406427088416270521091724287664
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 2494224121 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 2494267598 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2494267598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
22.sysrst_ctrl_stress_all_with_rand_reset.26349438708364776109980931944471844472294591328038146151181381445671488217754
Line 405, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16004410074 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 16004591891 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 16004591891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_edge_detect has 1 failures.
23.sysrst_ctrl_edge_detect.19950437005847773433018332573975221949188822288676530078928629619716823802401
Line 386, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_edge_detect/latest/run.log
UVM_ERROR @ 2209077515 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 2209098348 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2209098348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 4 failures:
1.sysrst_ctrl_ultra_low_pwr.100796159300423522107313903196519528322652712285368008763991909969270775534935
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 1147690354028 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 2293392854028 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2293392854028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.sysrst_ctrl_ultra_low_pwr.83814332663762386651121802906564558501638991999785634248163640155792412276397
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 2237154084 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 2274654084 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
UVM_INFO @ 5329654084 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
UVM_INFO @ 6734654084 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 6748190135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 2 more failures.
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 3 failures:
23.sysrst_ctrl_combo_detect_with_pre_cond.24528922072586880764889429177618036416591145563074934141452758686981888311370
Line 459, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 114662190670 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 114662190670 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 114662190670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.sysrst_ctrl_combo_detect_with_pre_cond.86604129444540874572453116354389506837235195883300781017747841889275198729656
Line 423, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 38265872835 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 38490872835 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 38510872835 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 48626303371 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x31
UVM_INFO @ 48626323779 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x22
... and 1 more failures.
UVM_ERROR (sysrst_ctrl_combo_detect_vseq.sv:239) [sysrst_ctrl_combo_detect_vseq] Check failed rdata == intr_actions (* [*] vs * [*]) has 1 failures:
17.sysrst_ctrl_stress_all.4543917347236408324907071279033817844874534863482087485475320846461714879629
Line 390, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 22126362942 ps: (sysrst_ctrl_combo_detect_vseq.sv:239) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Check failed rdata == intr_actions (4 [0x4] vs 5 [0x5])
UVM_ERROR @ 22151362942 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: 0x0
UVM_INFO @ 22151362942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_pin_override_vseq.sv:27) [sysrst_ctrl_pin_override_vseq] Check failed out_val == * (* [*] vs * [*]) has 1 failures:
48.sysrst_ctrl_stress_all_with_rand_reset.56645828686679867603706314094361118750791115320811626065629677072586548665113
Line 428, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7476150426 ps: (sysrst_ctrl_pin_override_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_override_vseq] Check failed out_val == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 7479801508 ps: (cip_base_vseq.sv:1166) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
Stress w/ reset is done for run 7/10
UVM_INFO @ 7485177856 ps: (cip_base_vseq.sv:1097) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 8/10
UVM_INFO @ 7485177856 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_errors_vseq 1/296
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 1 failures:
65.sysrst_ctrl_combo_detect_with_pre_cond.67033910313422707889283139328190535024642097392442143748382392635968078272058
Line 396, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/65.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 24686196812 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 24686196812 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 24686196812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:545) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 1 failures:
89.sysrst_ctrl_combo_detect_with_pre_cond.87751964543044638163185716155040988253767377908635615282095953699875621876803
Line 400, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/89.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 23652482993 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:545) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 0 (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 23652482993 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:561) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 23652482993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-* has 1 failures:
99.sysrst_ctrl_combo_detect_with_pre_cond.115061933071764319047859053901044471557202036253974634742897746538905285547464
Line 397, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/99.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 25205097400 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-4
UVM_ERROR @ 25205097400 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(6) vs exp(2) +/-4
UVM_INFO @ 25205097400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---