ADC_CTRL Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: `f01486e`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	20.340s	5.757ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.220s	1.008ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.810s	491.113us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	3.024m	44.931ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.140s	1.137ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	3.120s	520.333us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.810s	491.113us	20	20	100.00
		adc_ctrl_csr_aliasing	5.140s	1.137ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	18.553m	497.023ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	21.456m	488.273ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.055m	503.192ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.978m	489.047ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	28.357m	672.413ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	22.711m	609.737ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	23.433m	530.151ms	47	50	94.00
V2	clock_gating	adc_ctrl_clock_gating	25.075m	2.000s	26	50	52.00
V2	poweron_counter	adc_ctrl_poweron_counter	15.990s	5.020ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.043m	36.794ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	6.034m	119.726ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	54.888m	10.000s	44	50	88.00
V2	alert_test	adc_ctrl_alert_test	2.600s	520.782us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	2.400s	452.545us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.380s	714.345us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.380s	714.345us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.220s	1.008ms	5	5	100.00
		adc_ctrl_csr_rw	2.810s	491.113us	20	20	100.00
		adc_ctrl_csr_aliasing	5.140s	1.137ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.040s	5.178ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.220s	1.008ms	5	5	100.00
		adc_ctrl_csr_rw	2.810s	491.113us	20	20	100.00
		adc_ctrl_csr_aliasing	5.140s	1.137ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.040s	5.178ms	20	20	100.00
V2		TOTAL			707	740	95.54
V2S	tl_intg_err	adc_ctrl_sec_cm	17.880s	8.486ms	5	5	100.00
		adc_ctrl_tl_intg_err	27.960s	8.485ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	27.960s	8.485ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	25.825m	10.000s	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			883	920	95.98

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.32	99.05	95.99	100.00	100.00	98.64	95.95	91.63

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 23 failures:

Test adc_ctrl_clock_gating has 16 failures.

7.adc_ctrl_clock_gating.107127901899870797880205372808877739597759748788506086350091217078974914626531
Line 153, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest/run.log

  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.adc_ctrl_clock_gating.54925838052023597408007120910925796042847105266535963157924649459328564633397
Line 153, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest/run.log

  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 14 more failures.

Test adc_ctrl_stress_all has 4 failures.

17.adc_ctrl_stress_all.68855887306514116831986176732120886294087470959241225106347653289751876310078
Line 181, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.adc_ctrl_stress_all.47504830772378272697383128152669776309706202633858729197482594499107292700591
Line 167, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
- 30.adc_ctrl_stress_all_with_rand_reset.53817558967645710002892925193126958343962291358060390488848976442587448331145
  Line 217, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test adc_ctrl_filters_both has 2 failures.

32.adc_ctrl_filters_both.28573153640358356976056351995635658907628219009071995139008969783661594444645
Line 180, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/32.adc_ctrl_filters_both/latest/run.log

  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.adc_ctrl_filters_both.1188886661897504232201995532333083370438926692370774228215908003457098574435
Line 180, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/48.adc_ctrl_filters_both/latest/run.log

  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 12 failures:

Test adc_ctrl_clock_gating has 8 failures.

2.adc_ctrl_clock_gating.87906692962156201992310197490789837232260445816826912519782798109855309069343
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 2523597131 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 2523597131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.adc_ctrl_clock_gating.62238618315041938089788839644832562666573205278861846128607202881131745416733
Line 170, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 173121387644 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 173121387644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test adc_ctrl_stress_all has 2 failures.

22.adc_ctrl_stress_all.84178611631350053323505800075207049316346081483400590662454047206711616988218
Line 187, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 344769271575 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 344769271575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.adc_ctrl_stress_all.9559551911244663656339387441526176130477041743835394651106816879988543384361
Line 244, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 30709333838 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 30709333838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all_with_rand_reset has 2 failures.

43.adc_ctrl_stress_all_with_rand_reset.107783103418053733765327520558105886919504643237002110778401801328884729267324
Line 197, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 28156718838 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 28156718838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.adc_ctrl_stress_all_with_rand_reset.109574116265550312026270140025738977112114959130429530251315156208315660595846
Line 240, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 337410724227 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 337410724227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 43.adc_ctrl_filters_both.29018452297671197370314462358973983836106619150132248498419579914570803749833
    Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/43.adc_ctrl_filters_both/latest/run.log
```
  UVM_ERROR @ 78701136325 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 78701136325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (adc_ctrl_scoreboard.sv:137) [scoreboard] Check failed m_wakeup == m_expected_wakeup (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 47.adc_ctrl_stress_all_with_rand_reset.35974874797109380530669501550898565209533972972525870289276836239846244939148
    Line 183, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 95171303723 ps: (adc_ctrl_scoreboard.sv:137) [uvm_test_top.env.scoreboard] Check failed m_wakeup == m_expected_wakeup (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 95171303723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```